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kernel: SigSpec use more const& + overloads to prevent implicit SigSpec

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This commit is contained in:
Eddie Hung 2020-03-13 08:17:39 -07:00
parent b567f03c26
commit 432a09af80
14 changed files with 96 additions and 82 deletions
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2
passes/techmap/extract_reduce.cc
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@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass
SigSpec input;
for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0)
input.append_bit(b);
input.append(b);
SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);

2
passes/techmap/flowmap.cc
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@ -1405,7 +1405,7 @@ struct FlowmapWorker
RTLIL::SigSpec lut_a, lut_y = node;
for (auto input_node : input_nodes)
lut_a.append_bit(input_node);
lut_a.append(input_node);
lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);

4
passes/techmap/techmap.cc
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@ -906,8 +906,8 @@ struct TechmapWorker
RTLIL::SigSig port_conn;
for (auto &it : port_connmap) {
port_conn.first.append_bit(it.first);
port_conn.second.append_bit(it.second);
port_conn.first.append(it.first);
port_conn.second.append(it.second);
}
tpl->connect(port_conn);