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Blackboxes

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This commit is contained in:
Eddie Hung 2019-05-26 11:32:02 -07:00
parent 3981eba999
commit 4311b9b583
2 changed files with 10 additions and 10 deletions
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10
techlibs/xilinx/abc.box
View file

@ -3,18 +3,18 @@
# F7BMUX slower than F7AMUX # F7BMUX slower than F7AMUX
# Inputs: I0 I1 S0 # Inputs: I0 I1 S0
# Outputs: O # Outputs: O
F7BMUX 1 1 3 1 F7BMUX 1 0 3 1
217 223 296 217 223 296
# Inputs: I0 I1 S0 # Inputs: I0 I1 S0
# Outputs: O # Outputs: O
MUXF8 2 1 3 1 MUXF8 2 0 3 1
104 94 273 104 94 273
# CARRY4 + CARRY4_[ABCD]X # CARRY4 + CARRY4_[ABCD]X
# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
CARRY4 3 1 10 8 CARRY4 3 0 10 8
271 536 379 - - - 340 - - - 271 536 379 - - - 340 - - -
157 494 465 445 - - 433 469 - - 157 494 465 445 - - 433 469 - -
228 592 540 520 356 - 512 548 292 - 228 592 540 520 356 - 512 548 292 -
@ -27,13 +27,13 @@ CARRY4 3 1 10 8
# SLICEM/A6LUT # SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO # Outputs: DPO SPO
RAM64X1D 4 1 15 2 RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - - - - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - - 124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX # SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO # Outputs: DPO SPO
RAM128X1D 5 1 17 2 RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - - - - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - - 347 347 347 347 347 347 296 - - - - - - - - - -

10
techlibs/xilinx/cells_sim.v
View file

@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S);
assign O = S ? CI : DI; assign O = S ? CI : DI;
endmodule endmodule
(* abc_box_id = 1, lib_whitebox *) (* abc_box_id = 1 /*, lib_whitebox*/ *)
module MUXF7(output O, input I0, I1, S); module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0; assign O = S ? I1 : I0;
endmodule endmodule
(* abc_box_id = 2, lib_whitebox *) (* abc_box_id = 2 /*, lib_whitebox*/ *)
module MUXF8(output O, input I0, I1, S); module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0; assign O = S ? I1 : I0;
endmodule endmodule
@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI; assign O = CI ^ LI;
endmodule endmodule
(* abc_box_id = 3, lib_whitebox *) (* abc_box_id = 3 /*, lib_whitebox*/ *)
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
assign O = S ^ {CO[2:0], CI | CYINIT}; assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
(* abc_box_id = 4, lib_whitebox *) (* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D ( module RAM64X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -301,7 +301,7 @@ module RAM64X1D (
`endif `endif
endmodule endmodule
(* abc_box_id = 5, lib_whitebox *) (* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D ( module RAM128X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,