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https://github.com/YosysHQ/yosys
synced 2025-08-03 01:40:23 +00:00
Move ABC pass state to a struct instead of storing it in global variables.
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262b00d5e5
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1 changed files with 62 additions and 62 deletions
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@ -113,23 +113,42 @@ bool map_mux8;
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bool map_mux16;
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bool markgroups;
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int map_autoidx;
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SigMap assign_map;
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RTLIL::Module *module;
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std::vector<gate_t> signal_list;
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dict<RTLIL::SigBit, int> signal_map;
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FfInitVals initvals;
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pool<std::string> enabled_gates;
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bool cmos_cost;
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bool had_init;
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bool clk_polarity, en_polarity, arst_polarity, srst_polarity;
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RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
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dict<int, std::string> pi_map, po_map;
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struct AbcModuleState {
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int map_autoidx = 0;
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SigMap assign_map;
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RTLIL::Module *module = nullptr;
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std::vector<gate_t> signal_list;
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dict<RTLIL::SigBit, int> signal_map;
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FfInitVals initvals;
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bool had_init = false;
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int undef_bits_lost;
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bool clk_polarity = false;
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bool en_polarity = false;
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bool arst_polarity = false;
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bool srst_polarity = false;
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RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
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dict<int, std::string> pi_map, po_map;
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
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int undef_bits_lost = 0;
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
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void mark_port(RTLIL::SigSpec sig);
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void extract_cell(RTLIL::Cell *cell, bool keepff);
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std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr);
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void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts);
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void handle_loops();
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::vector<std::string> &liberty_files, std::vector<std::string> &genlib_files, std::string constr_file,
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bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target,
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std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector<std::string> &dont_use_cells);
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};
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int AbcModuleState::map_signal(RTLIL::SigBit bit, gate_type_t gate_type, int in1, int in2, int in3, int in4)
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{
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assign_map.apply(bit);
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@ -167,14 +186,14 @@ int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1,
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return gate.id;
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}
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void mark_port(RTLIL::SigSpec sig)
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void AbcModuleState::mark_port(RTLIL::SigSpec sig)
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{
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for (auto &bit : assign_map(sig))
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if (bit.wire != nullptr && signal_map.count(bit) > 0)
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signal_list[signal_map[bit]].is_port = true;
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}
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void extract_cell(RTLIL::Cell *cell, bool keepff)
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void AbcModuleState::extract_cell(RTLIL::Cell *cell, bool keepff)
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{
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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FfData ff(&initvals, cell);
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@ -377,7 +396,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
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}
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}
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std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
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std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire)
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{
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std::string abc_sname = abc_name.substr(1);
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bool isnew = false;
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@ -416,7 +435,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
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return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
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}
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void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts)
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void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts)
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{
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if (f == nullptr)
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return;
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@ -445,7 +464,7 @@ void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &w
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fprintf(f, "}\n");
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}
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void handle_loops()
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void AbcModuleState::handle_loops()
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{
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// http://en.wikipedia.org/wiki/Topological_sorting
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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@ -646,13 +665,15 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
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struct abc_output_filter
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{
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const AbcModuleState &state;
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bool got_cr;
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int escape_seq_state;
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std::string linebuf;
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std::string tempdir_name;
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bool show_tempdir;
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abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
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abc_output_filter(const AbcModuleState& state, std::string tempdir_name, bool show_tempdir)
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: state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir)
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{
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got_cr = false;
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escape_seq_state = 0;
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@ -693,8 +714,8 @@ struct abc_output_filter
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int pi, po;
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if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
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log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
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pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
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po, po_map.count(po) ? po_map.at(po).c_str() : "???");
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pi, state.pi_map.count(pi) ? state.pi_map.at(pi).c_str() : "???",
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po, state.po_map.count(po) ? state.po_map.at(po).c_str() : "???");
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return;
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}
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@ -703,20 +724,16 @@ struct abc_output_filter
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}
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};
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::vector<std::string> &liberty_files, std::vector<std::string> &genlib_files, std::string constr_file,
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bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target,
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std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector<std::string> &dont_use_cells)
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{
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module = current_module;
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initvals.set(&assign_map, module);
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map_autoidx = autoidx++;
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signal_map.clear();
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signal_list.clear();
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pi_map.clear();
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po_map.clear();
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if (clk_str != "$")
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{
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clk_polarity = true;
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@ -1109,7 +1126,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
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#ifndef YOSYS_LINK_ABC
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abc_output_filter filt(tempdir_name, show_tempdir);
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abc_output_filter filt(*this, tempdir_name, show_tempdir);
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int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
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#else
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string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str());
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@ -1652,13 +1669,6 @@ struct AbcPass : public Pass {
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log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
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log_push();
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assign_map.clear();
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signal_list.clear();
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signal_map.clear();
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initvals.clear();
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pi_map.clear();
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po_map.clear();
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std::string exe_file = yosys_abc_executable;
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std::string script_file, default_liberty_file, constr_file, clk_str;
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std::vector<std::string> liberty_files, genlib_files, dont_use_cells;
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@ -1667,13 +1677,6 @@ struct AbcPass : public Pass {
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bool show_tempdir = false, sop_mode = false;
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bool abc_dress = false;
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vector<int> lut_costs;
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markgroups = false;
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map_mux4 = false;
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map_mux8 = false;
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map_mux16 = false;
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enabled_gates.clear();
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cmos_cost = false;
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// get arguments from scratchpad first, then override by command arguments
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std::string lut_arg, luts_arg, g_arg;
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@ -2049,11 +2052,10 @@ struct AbcPass : public Pass {
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continue;
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}
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assign_map.set(mod);
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initvals.set(&assign_map, mod);
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if (!dff_mode || !clk_str.empty()) {
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abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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AbcModuleState state;
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state.assign_map.set(mod);
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state.abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress, dont_use_cells);
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continue;
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}
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@ -2074,6 +2076,10 @@ struct AbcPass : public Pass {
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
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dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
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SigMap assign_map;
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assign_map.set(mod);
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FfInitVals initvals;
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initvals.set(&assign_map, mod);
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for (auto cell : all_cells)
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{
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clkdomain_t key;
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@ -2207,27 +2213,21 @@ struct AbcPass : public Pass {
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std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
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for (auto &it : assigned_cells) {
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clk_polarity = std::get<0>(it.first);
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clk_sig = assign_map(std::get<1>(it.first));
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en_polarity = std::get<2>(it.first);
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en_sig = assign_map(std::get<3>(it.first));
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arst_polarity = std::get<4>(it.first);
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arst_sig = assign_map(std::get<5>(it.first));
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srst_polarity = std::get<6>(it.first);
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srst_sig = assign_map(std::get<7>(it.first));
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abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
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AbcModuleState state;
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state.assign_map.set(mod);
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state.clk_polarity = std::get<0>(it.first);
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state.clk_sig = assign_map(std::get<1>(it.first));
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state.en_polarity = std::get<2>(it.first);
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state.en_sig = assign_map(std::get<3>(it.first));
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state.arst_polarity = std::get<4>(it.first);
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state.arst_sig = assign_map(std::get<5>(it.first));
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state.srst_polarity = std::get<6>(it.first);
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state.srst_sig = assign_map(std::get<7>(it.first));
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state.abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !state.clk_sig.empty(), "$",
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keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress, dont_use_cells);
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assign_map.set(mod);
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}
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}
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assign_map.clear();
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signal_list.clear();
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signal_map.clear();
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initvals.clear();
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pi_map.clear();
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po_map.clear();
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log_pop();
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}
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} AbcPass;
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