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OUT port to Y in generic DSP

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This commit is contained in:
Eddie Hung 2019-07-15 14:45:47 -07:00
parent 0c7ee6d0fa
commit 42f8e68e76
2 changed files with 3 additions and 3 deletions
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2
techlibs/common/mul2dsp.v
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@ -209,7 +209,7 @@ module \$__mul_gen (A, B, Y);
`DSP_NAME _TECHMAP_REPLACE_ (
.A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),
.B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),
.OUT({dummy, out})
.Y({dummy, out})
);
if (Y_WIDTH < A_WIDTH+B_WIDTH)
assign Y = out[Y_WIDTH-1:0];