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Added very first version of "synth_ice40"

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Clifford Wolf 2015-03-05 20:37:55 +01:00
parent ed15400fc6
commit 42d5d94a5d
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techlibs/ice40/cells_sim.v Normal file
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module SB_LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module SB_DFF (output reg Q, input C, D);
always @(posedge C)
Q <= D;
endmodule