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https://github.com/YosysHQ/yosys
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move outside of VERIFIC_SYSTEMVERILOG_SUPPORT
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parent
18d66b96f9
commit
42c9b9ef68
1 changed files with 2 additions and 4 deletions
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@ -3074,7 +3074,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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Netlist *nl = it->second;
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// use Verific optimizations
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (verific_opt) {
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log(" Running Verific optimizations for %s.\n", it->first.c_str());
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@ -3084,7 +3083,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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log(" Running operator optimization for %s.\n", it->first.c_str());
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nl->OperatorOptimization();
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}
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#endif
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if (nl_done.count(it->first) == 0) {
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VerificImporter importer(false, false, false, false, false, false, false, false);
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@ -3707,12 +3705,12 @@ struct VerificPass : public Pass {
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break;
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}
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (GetSize(args) > argidx && args[argidx] == "-optimization") {
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verific_opt = true;
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continue;
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goto check_error;
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}
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
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{
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unsigned verilog_mode = veri_file::UNDEFINED;
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