mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

opt_clean: handle undriven and x-bit driven bits consistently

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-04-08 23:49:15 +02:00
parent 0c689091e2
commit 42c0f9f3a6
2 changed files with 38 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

30
passes/opt/opt_clean.cc
View file

@ -31,6 +31,24 @@ PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr; using RTLIL::id2cstr;
struct CleanerPool : SigPool
{
bool check_all_def(const RTLIL::SigSpec &sig) const
{
for (auto &bit : sig) {
if (bit.wire != NULL && bits.count(bit) == 0)
return false;
if (bit.wire == NULL && bit.data == RTLIL::State::Sx)
return false;
}
return true;
}
bool check_def(const RTLIL::SigBit &bit) const
{
return (bit.wire != NULL && bits.count(bit)) || (bit.wire == NULL && bit.data != RTLIL::State::Sx);
}
};
struct keep_cache_t struct keep_cache_t
{ {
Design *design; Design *design;
@ -356,7 +374,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
// used signals pre-sigmapped // used signals pre-sigmapped
SigPool raw_used_signals; SigPool raw_used_signals;
// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`) // used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
SigPool used_signals_nodrivers; CleanerPool used_signals_nodrivers;
// gather the usage information for cells // gather the usage information for cells
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
@ -472,14 +490,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
module->connect(new_conn); module->connect(new_conn);
} }
if (!used_signals_nodrivers.check_all(s2)) { if (!used_signals_nodrivers.check_all_def(s2)) {
std::string unused_bits; std::string unused_bits;
for (int i = 0; i < GetSize(s2); i++) { for (int i = 0; i < GetSize(s2); i++) {
if (s2[i].wire == NULL) if ((s2[i].wire == NULL) && (s2[i].data != RTLIL::State::Sx))
continue; continue;
if (!used_signals_nodrivers.check(s2[i])) { if (!used_signals_nodrivers.check_def(s2[i])) {
if (!unused_bits.empty()) if (!unused_bits.empty())
unused_bits += " "; unused_bits += " ";
unused_bits += stringf("%d", i); unused_bits += stringf("%d", i);
} }
} }

14
tests/opt/opt_clean_x.ys Normal file
View file

@ -0,0 +1,14 @@
read_verilog <<EOT
module alu(
);
wire [1:0] p1, p2;
assign p1 = 2'bx1;
assign p2[0] = 1'b1;
endmodule
EOT
proc
opt_clean
dump
select -assert-count 1 w:p1 a:unused_bits=1 %i
select -assert-count 1 w:p2 a:unused_bits=1 %i