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machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.

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William D. Jones 2020-11-20 18:53:09 -05:00 • committed by Marcelina Kościelnicka
parent 19b043344c
commit 427fed23ee
2 changed files with 4 additions and 4 deletions
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4
techlibs/machxo2/cells_map.v
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@ -17,11 +17,11 @@ module \$lut (A, Y);
end else if(WIDTH == 4) begin end else if(WIDTH == 4) begin
assign I = {A[3], A[2], A[1], A[0]}; assign I = {A[3], A[2], A[1], A[0]};
end else begin end else begin
INVALID_LUT_WIDTH error(); wire _TECHMAP_FAIL_ = 1;
end end
endgenerate endgenerate
LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .F(Y)); LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
endmodule endmodule
module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule

4
techlibs/machxo2/cells_sim.v
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@ -2,7 +2,7 @@ module LUT4 #(
parameter [15:0] INIT = 0 parameter [15:0] INIT = 0
) ( ) (
input A, B, C, D, input A, B, C, D,
output F output Z
); );
wire [3:0] I; wire [3:0] I;
wire [3:0] I_pd; wire [3:0] I_pd;
@ -14,7 +14,7 @@ module LUT4 #(
endgenerate endgenerate
assign I = {D, C, B, A}; assign I = {D, C, B, A};
assign F = INIT[I_pd]; assign Z = INIT[I_pd];
endmodule endmodule
module FACADE_FF #( module FACADE_FF #(