From 426ef53c205a0c5de14dbcb821363ac3e04d5ba4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 5 Nov 2024 09:14:15 +0100
Subject: [PATCH] Document `gate_cost_equivalent`

---
 README.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/README.md b/README.md
index 3845d2502..3bcd59ec8 100644
--- a/README.md
+++ b/README.md
@@ -575,6 +575,9 @@ Non-standard or SystemVerilog features for formal verification
   ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
   is marked with the ``(* gclk *)`` Verilog attribute.
 
+- The `gate_cost_equivalent` attribute on a module can be used to specify
+  the estimated cost of a module as an equivalent number of basic gate
+  instances.
 
 Supported features from SystemVerilog
 =====================================