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https://github.com/YosysHQ/yosys
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WIP half broken snapshot
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parent
30505c2cd6
commit
423c8be71b
11 changed files with 1225 additions and 62 deletions
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@ -50,21 +50,25 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections,
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}
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bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
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// Removing $connect and $input_port doesn't count as "doing something"
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// since they get rebuilt in signorm
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// and don't enable further opt
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bool did_something = false;
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for (RTLIL::Cell *cell : cells) {
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if (verbose) {
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if (cell->type == ID($connect))
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if (cell->type == ID($connect)) {
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log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
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log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
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else if (cell->type == ID($input_port))
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} else if (cell->type == ID($input_port)) {
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log_debug(" removing input port marker cell `%s': %s\n", cell->name,
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log_signal(cell->getPort(ID::Y)));
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else
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} else {
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did_something = true;
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log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
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log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
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}
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}
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mod->remove(cell);
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did_something = true;
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}
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return did_something;
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}
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@ -77,6 +77,8 @@ struct OptCleanPass : public Pass {
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}
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extra_args(args, argidx, design);
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design->sigNormalize(false);
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{
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std::vector<RTLIL::Module*> selected_modules;
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for (auto module : design->selected_whole_modules_warn())
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@ -128,6 +130,8 @@ struct CleanPass : public Pass {
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}
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extra_args(args, argidx, design);
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design->sigNormalize(false);
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{
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std::vector<RTLIL::Module*> selected_modules;
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for (auto module : design->selected_unboxed_whole_modules())
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@ -576,8 +576,8 @@ bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::
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if (clean_ctx.flags.verbose && deleted_and_unreported)
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log_debug(" removed %d unused temporary wires.\n", deleted_and_unreported);
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if (deleted_total)
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module->design->scratchpad_set_bool("opt.did_something", true);
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// if (deleted_total)
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// module->design->scratchpad_set_bool("opt.did_something", true);
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return deleted_total != 0;
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}
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