WIP half broken snapshot

passes/opt/Makefile.inc

@@ -1,6 +1,7 @@
 
 OBJS += passes/opt/opt.o
 OBJS += passes/opt/opt_merge.o
+OBJS += passes/opt/opt_merge_inc.o
 OBJS += passes/opt/opt_mem.o
 OBJS += passes/opt/opt_mem_feedback.o
 OBJS += passes/opt/opt_mem_priority.o

passes/opt/opt_clean/cells_temp.cc

@@ -50,21 +50,25 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections,
 }
 
 bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
+	// Removing $connect and $input_port doesn't count as "doing something"
+	// since they get rebuilt in signorm
+	// and don't enable further opt
 	bool did_something = false;
 	for (RTLIL::Cell *cell : cells) {
 		if (verbose) {
-			if (cell->type == ID($connect))
+			if (cell->type == ID($connect)) {
 				log_debug("  removing connect cell `%s': %s <-> %s\n", cell->name,
 						log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
-			else if (cell->type == ID($input_port))
+			} else if (cell->type == ID($input_port)) {
 				log_debug("  removing input port marker cell `%s': %s\n", cell->name,
 						log_signal(cell->getPort(ID::Y)));
-			else
+			} else {
+				did_something = true;
 				log_debug("  removing buffer cell `%s': %s = %s\n", cell->name,
 						log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
+			}
 		}
 		mod->remove(cell);
-		did_something = true;
 	}
 	return did_something;
 }

passes/opt/opt_clean/opt_clean.cc

@@ -77,6 +77,8 @@ struct OptCleanPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(false);
+
 		{
 			std::vector<RTLIL::Module*> selected_modules;
 			for (auto module : design->selected_whole_modules_warn())
@@ -128,6 +130,8 @@ struct CleanPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(false);
+
 		{
 			std::vector<RTLIL::Module*> selected_modules;
 			for (auto module : design->selected_unboxed_whole_modules())

passes/opt/opt_clean/wires.cc

@@ -576,8 +576,8 @@ bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::
 	if (clean_ctx.flags.verbose && deleted_and_unreported)
 		log_debug("  removed %d unused temporary wires.\n", deleted_and_unreported);
 
-	if (deleted_total)
-		module->design->scratchpad_set_bool("opt.did_something", true);
+	// if (deleted_total)
+	// 	module->design->scratchpad_set_bool("opt.did_something", true);
 
 	return deleted_total != 0;
 }

passes/opt/opt_expr.cc

@@ -392,12 +392,15 @@ int get_highest_hot_index(RTLIL::SigSpec signal)
 	return -1;
 }
 
-void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv, int timestamp=INT_MIN)
 {
-	SigMap assign_map(module);
+	SigMap assign_map; //(module);
 	dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
 
-	for (auto cell : module->cells()) {
+
+	auto dirty_cells = module->dirty_cells(timestamp);
+
+	for (auto cell : dirty_cells) {
 		if (design->selected(module, cell) && cell->type[0] == '$') {
 			if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
 					GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
@@ -409,7 +412,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	}
 
 	if (!noclkinv)
-	for (auto cell : module->cells())
+	for (auto cell : dirty_cells)
 	if (design->selected(module, cell)) {
 		if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
 			handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
@@ -487,9 +490,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	}
 
 	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
+
 	dict<RTLIL::SigBit, Cell*> outbit_to_cell;
 
-	for (auto cell : module->cells())
+	for (auto cell : dirty_cells)
 	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
 		for (auto &conn : cell->connections())
 		if (yosys_celltypes.cell_output(cell->type, conn.first))
@@ -498,7 +502,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		cells.node(cell);
 	}
 
-	for (auto cell : module->cells())
+	for (auto cell : dirty_cells)
 	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
 		const int r_index = cells.node(cell);
 		for (auto &conn : cell->connections())
@@ -514,6 +518,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", module);
 	}
 
+	log("iterating over %d cells\n", GetSize(cells.sorted));
+
 	for (auto cell : cells.sorted)
 	{
 #define ACTION_DO(_p_, _s_) do { replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
@@ -1144,10 +1150,10 @@ skip_fine_alu:
 			if (input.match("  1")) ACTION_DO(ID::Y, input.extract(1, 1));
 			if (input.match("01 ")) ACTION_DO(ID::Y, input.extract(0, 1));
 			if (input.match("10 ")) {
-				cell->type = ID($_NOT_);
 				cell->setPort(ID::A, input.extract(0, 1));
 				cell->unsetPort(ID::B);
 				cell->unsetPort(ID::S);
+				cell->type = ID($_NOT_);
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -1242,10 +1248,10 @@ skip_fine_alu:
 					ACTION_DO(ID::Y, cell->getPort(ID::A));
 				} else {
 					log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
-					cell->type = ID($not);
 					cell->parameters.erase(ID::B_WIDTH);
 					cell->parameters.erase(ID::B_SIGNED);
 					cell->unsetPort(ID::B);
+					cell->type = ID($not);
 					did_something = true;
 				}
 				goto next_cell;
@@ -1257,7 +1263,6 @@ skip_fine_alu:
 		{
 			log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
 					module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
-			cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
 			if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
 				cell->setPort(ID::A, cell->getPort(ID::B));
 				cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
@@ -1266,6 +1271,7 @@ skip_fine_alu:
 			cell->unsetPort(ID::B);
 			cell->unsetParam(ID::B_SIGNED);
 			cell->unsetParam(ID::B_WIDTH);
+			cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
 			did_something = true;
 			goto next_cell;
 		}
@@ -1408,10 +1414,10 @@ skip_fine_alu:
 					cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
 				}
 
-				cell->type = arith_inverse ? ID($neg) : ID($pos);
 				cell->unsetPort(ID::B);
 				cell->parameters.erase(ID::B_WIDTH);
 				cell->parameters.erase(ID::B_SIGNED);
+				cell->type = arith_inverse ? ID($neg) : ID($pos);
 				cell->check();
 
 				did_something = true;
@@ -2292,9 +2298,14 @@ struct OptExprPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(true);
+
 		NewCellTypes ct(design);
 		for (auto module : design->selected_modules())
 		{
+
+			int replace_const_cells_timestamp = INT_MIN;
+			int replace_const_cells_consume_x_timestamp = INT_MIN;
 			log("Optimizing module %s.\n", module);
 
 			if (undriven) {
@@ -2307,12 +2318,17 @@ struct OptExprPass : public Pass {
 			do {
 				do {
 					did_something = false;
-					replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
+					module->next_timestamp();
+					replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, replace_const_cells_timestamp);
+					replace_const_cells_timestamp = module->timestamp();
 					if (did_something)
 						design->scratchpad_set_bool("opt.did_something", true);
 				} while (did_something);
-				if (!keepdc)
-					replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
+				if (!keepdc) {
+					module->next_timestamp();
+					replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, replace_const_cells_consume_x_timestamp);
+					replace_const_cells_consume_x_timestamp = module->timestamp();
+				}
 				if (did_something)
 					design->scratchpad_set_bool("opt.did_something", true);
 			} while (did_something);

passes/opt/opt_merge.cc

@@ -497,7 +497,7 @@ struct OptMergeWorker
 };
 
 struct OptMergePass : public Pass {
-	OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
+	OptMergePass() : Pass("opt_merge_old", "consolidate identical cells") { }
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

passes/opt/opt_merge_inc.cc

@@ -0,0 +1,608 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/ffinit.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include "kernel/celltypes.h"
+#include "libs/sha1/sha1.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include <algorithm>
+#include <set>
+#include <unordered_map>
+#include <array>
+
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+template <typename T, typename U>
+inline Hasher hash_pair(const T &t, const U &u) { return hash_ops<std::pair<T, U>>::hash(t, u); }
+
+struct OptMergeIncWorker
+{
+	RTLIL::Design *design;
+	RTLIL::Module *module;
+	SigMap assign_map;
+	FfInitVals initvals;
+	bool mode_share_all;
+
+	CellTypes ct;
+	int total_count;
+
+	static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h)
+	{
+		int s_width = GetSize(sig_s);
+		int width = GetSize(sig_b) / s_width;
+
+		hashlib::commutative_hash comm;
+		for (int i = 0; i < s_width; i++)
+			comm.eat(hash_pair(sig_s[i], sig_b.extract(i*width, width)));
+
+		return comm.hash_into(h);
+	}
+
+	static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
+	{
+		SigSpec sig_s = conn.at(ID::S);
+		SigSpec sig_b = conn.at(ID::B);
+
+		int s_width = GetSize(sig_s);
+		int width = GetSize(sig_b) / s_width;
+
+		vector<pair<SigBit, SigSpec>> sb_pairs;
+		for (int i = 0; i < s_width; i++)
+			sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
+
+		std::sort(sb_pairs.begin(), sb_pairs.end());
+
+		conn[ID::S] = SigSpec();
+		conn[ID::B] = SigSpec();
+
+		for (auto &it : sb_pairs) {
+			conn[ID::S].append(it.first);
+			conn[ID::B].append(it.second);
+		}
+	}
+
+	Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const
+	{
+		// TODO: when implemented, use celltypes to match:
+		// (builtin || stdcell) && (unary || binary) && symmetrical
+		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
+				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
+			hashlib::commutative_hash comm;
+			comm.eat((cell->getPort(ID::A)));
+			comm.eat((cell->getPort(ID::B)));
+			h = comm.hash_into(h);
+		} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			SigSpec a = (cell->getPort(ID::A));
+			a.sort();
+			h = a.hash_into(h);
+		} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+			SigSpec a = (cell->getPort(ID::A));
+			a.sort_and_unify();
+			h = a.hash_into(h);
+		} else if (cell->type == ID($pmux)) {
+			SigSpec sig_s = (cell->getPort(ID::S));
+			SigSpec sig_b = (cell->getPort(ID::B));
+			h = hash_pmux_in(sig_s, sig_b, h);
+			h = (cell->getPort(ID::A)).hash_into(h);
+		} else {
+			hashlib::commutative_hash comm;
+			for (const auto& [port, sig] : cell->connections()) {
+				if (cell->output(port))
+					continue;
+				comm.eat(hash_pair(port, (sig)));
+			}
+			h = comm.hash_into(h);
+			if (cell->is_builtin_ff())
+				h = initvals(cell->getPort(ID::Q)).hash_into(h);
+		}
+		return h;
+	}
+
+	static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
+	{
+		hashlib::commutative_hash comm;
+		for (const auto& param : cell->parameters) {
+			comm.eat(param);
+		}
+		return comm.hash_into(h);
+	}
+
+	Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const
+	{
+		h.eat(cell->type);
+		h = hash_cell_inputs(cell, h);
+		h = hash_cell_parameters(cell, h);
+		return h;
+	}
+
+	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const
+	{
+		if (cell1 == cell2) return true;
+		if (cell1->type != cell2->type) return false;
+
+		if (cell1->parameters != cell2->parameters)
+			return false;
+
+		if (cell1->connections_.size() != cell2->connections_.size())
+			return false;
+		for (const auto &it : cell1->connections_)
+			if (!cell2->connections_.count(it.first))
+				return false;
+
+		decltype(Cell::connections_) conn1, conn2;
+		conn1.reserve(cell1->connections_.size());
+		conn2.reserve(cell1->connections_.size());
+
+		for (const auto &it : cell1->connections_) {
+			if (cell1->output(it.first)) {
+				if (it.first == ID::Q && cell1->is_builtin_ff()) {
+					// For the 'Q' output of state elements,
+					//   use the (* init *) attribute value
+					conn1[it.first] = initvals(it.second);
+					conn2[it.first] = initvals(cell2->getPort(it.first));
+				}
+				else {
+					conn1[it.first] = RTLIL::SigSpec();
+					conn2[it.first] = RTLIL::SigSpec();
+				}
+			}
+			else {
+				conn1[it.first] = (it.second);
+				conn2[it.first] = (cell2->getPort(it.first));
+			}
+		}
+
+		if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
+				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
+			if (conn1.at(ID::A) < conn1.at(ID::B)) {
+				std::swap(conn1[ID::A], conn1[ID::B]);
+			}
+			if (conn2.at(ID::A) < conn2.at(ID::B)) {
+				std::swap(conn2[ID::A], conn2[ID::B]);
+			}
+		} else
+		if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			conn1[ID::A].sort();
+			conn2[ID::A].sort();
+		} else
+		if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+			conn1[ID::A].sort_and_unify();
+			conn2[ID::A].sort_and_unify();
+		} else
+		if (cell1->type == ID($pmux)) {
+			sort_pmux_conn(conn1);
+			sort_pmux_conn(conn2);
+		}
+
+		return conn1 == conn2;
+	}
+
+	bool has_dont_care_initval(const RTLIL::Cell *cell)
+	{
+		if (!cell->is_builtin_ff())
+			return false;
+
+		return !initvals(cell->getPort(ID::Q)).is_fully_def();
+	}
+
+	OptMergeIncWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) :
+		design(design), module(module), mode_share_all(mode_share_all)
+	{
+		total_count = 0;
+		ct.setup_internals();
+		ct.setup_internals_mem();
+		ct.setup_stdcells();
+		ct.setup_stdcells_mem();
+
+		if (mode_nomux) {
+			ct.cell_types.erase(ID($mux));
+			ct.cell_types.erase(ID($pmux));
+		}
+
+		ct.cell_types.erase(ID($tribuf));
+		ct.cell_types.erase(ID($_TBUF_));
+		ct.cell_types.erase(ID($anyseq));
+		ct.cell_types.erase(ID($anyconst));
+		ct.cell_types.erase(ID($allseq));
+		ct.cell_types.erase(ID($allconst));
+		ct.cell_types.erase(ID($connect));
+		ct.cell_types.erase(ID($input_port));
+
+		log("Finding identical cells in module `%s'.\n", module->name);
+		assign_map.set(module);
+
+		initvals.set(&assign_map, module);
+
+
+		// We keep a set of known cells. They're hashed with our hash_cell_function
+		// and compared with our compare_cell_parameters_and_connections.
+		// Both need to capture OptMergeIncWorker to access initvals
+		struct CellPtrHash {
+			const OptMergeIncWorker& worker;
+			CellPtrHash(const OptMergeIncWorker& w) : worker(w) {}
+			std::size_t operator()(const Cell* c) const {
+				return (std::size_t)worker.hash_cell_function(c, Hasher()).yield();
+			}
+		};
+		struct CellPtrEqual {
+			const OptMergeIncWorker& worker;
+			CellPtrEqual(const OptMergeIncWorker& w) : worker(w) {}
+			bool operator()(const Cell* lhs, const Cell* rhs) const {
+				return worker.compare_cell_parameters_and_connections(lhs, rhs);
+			}
+		};
+		// std::unordered_set<
+		//     RTLIL::Cell*,
+		//     CellPtrHash,
+		//     CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
+
+		dict<Cell *, uint32_t> hashes;
+		dict<uint32_t, Cell *> first_with_hash;
+		dict<uint32_t, pool<Cell *>> more_with_hash;
+
+		auto forget_cell = [&](Cell * cell) {
+			auto found = hashes.find(cell);
+			if (found != hashes.end()) {
+				auto found_first = first_with_hash.find(found->second);
+				log_assert(found_first != first_with_hash.end());
+				auto found_more = more_with_hash.find(found->second);
+				if (found_more != more_with_hash.end()) {
+					found_more->second.erase(cell);
+					found_first->second = *found_more->second.begin();
+					if (found_more->second.size() < 2)
+						more_with_hash.erase(found_more);
+				}
+
+				// auto found_first = first_with_hash.find(found->second);
+				// log_assert(found_first != first_with_hash.end());
+				// if (found_first->second == cell) {
+				// 	auto found_more = more_with_hash.find(found->second);
+				// 	if (found_more != more_with_hash.end()) {
+				// 		log_assert(!found_more->second.empty());
+				// 		found_first->second = found_more->second.pop();
+				// 		if (found_more->second.empty())
+				// 			more_with_hash.erase(found_more);
+
+				// 	} else {
+				// 		first_with_hash.erase(found_first);
+				// 	}
+
+				// } else {
+				// 	auto found_more = more_with_hash.find(found->second);
+				// 	if (found_more != more_with_hash.end()) {
+				// 		found_more->second.erase(cell);
+				// 		if (found_more->second.empty())
+				// 			more_with_hash.erase(found_more);
+				// 	}
+				// }
+			}
+		};
+
+		auto remember_cell = [&](Cell * cell, uint32_t hash) -> bool {
+			hashes[cell] = hash;
+			auto [it, inserted] = first_with_hash.emplace(hash, cell);
+			if (!inserted) {
+				auto &more = more_with_hash[hash];
+				if (more.empty())
+					more.emplace(it->second);
+				more.emplace(cell);
+			}
+			return !inserted;
+		};
+
+		int timestamp = INT_MIN;
+
+		bool did_something = true;
+		// A cell may have to go through a lot of collisions if the hash
+		// function is performing poorly, but it's a symptom of something bad
+		// beyond the user's control.
+
+		bool first = true;
+		while (did_something)
+		{
+			std::vector<RTLIL::Cell*> cells;
+
+			if (timestamp == INT_MIN) {
+				timestamp = module->next_timestamp();
+				cells.reserve(module->cells().size());
+				for (auto cell : module->cells()) {
+					if (!design->selected(module, cell))
+						continue;
+					if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+						// Ignore those for performance: meminit can have an excessively large port,
+						// mem can have an excessively large parameter holding the init data
+						continue;
+					}
+					if (cell->type == ID($scopeinfo))
+						continue;
+					if (mode_keepdc && has_dont_care_initval(cell))
+						continue;
+					if (!cell->known())
+						continue;
+					if (!mode_share_all && !ct.cell_known(cell->type))
+						continue;
+
+					cells.push_back(cell);
+				}
+			} else {
+				int next = module->next_timestamp();
+				// idict<Cell *> pending;
+				// for (auto cell : module->dirty_cells(timestamp))
+				//     pending(cell);
+				// std::vector<const pool<RTLIL::PortBit> *> fanouts;
+				// int i = 0;
+				// while (i < GetSize(pending)) {
+				//     Cell * cell = pending[i];
+				// pool<Cell *> pending;
+				for (auto cell : module->dirty_cells(timestamp)) {
+					if (!design->selected(module, cell))
+						continue;
+					if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+						// Ignore those for performance: meminit can have an excessively large port,
+						// mem can have an excessively large parameter holding the init data
+						continue;
+					}
+					if (cell->type == ID($scopeinfo))
+						continue;
+					if (mode_keepdc && has_dont_care_initval(cell))
+						continue;
+					if (!cell->known())
+						continue;
+					if (!mode_share_all && !ct.cell_known(cell->type))
+						continue;
+
+
+					cells.push_back(cell);
+				}
+				timestamp = next;
+			}
+			log("scanning %d cells\n", GetSize(cells));
+
+			did_something = false;
+
+			if (!first)
+				for (auto cell : cells)
+					forget_cell(cell);
+			first = false;
+
+
+			pool<int32_t> buckets;
+
+			for (auto cell : cells) {
+				uint32_t hash = hash_cell_function(cell, Hasher()).yield();
+				if (remember_cell(cell, hash))
+					buckets.emplace(hash);
+			}
+
+			std::vector<std::pair<Cell *, Cell*>> pairs;
+			pool<Cell *> removed;
+
+			log("scanning %d/%d/%d buckets\n", GetSize(buckets), GetSize(more_with_hash), GetSize(first_with_hash));
+			for (auto hash : buckets) {
+				auto more = more_with_hash.at(hash);
+
+				for (int i = 0; i < GetSize(more); ++i) {
+					for (int j = i + 1; j < GetSize(more); ++j) {
+						Cell *other_cell = *more.element(j);
+						if (removed.count(other_cell))
+							continue;
+						Cell *cell = *more.element(i);
+						if (removed.count(cell))
+							break;
+
+						if (!compare_cell_parameters_and_connections(cell, other_cell))
+							continue;
+
+						if (cell->has_keep_attr()) {
+							if (other_cell->has_keep_attr())
+								continue;
+							std::swap(cell, other_cell);
+						}
+
+						removed.insert(cell);
+						pairs.emplace_back(other_cell, cell);
+					}
+
+				}
+			}
+
+			for (auto cell : removed)
+				forget_cell(cell);
+
+			int iter_count = 0;
+
+			for (auto [other_cell, cell] : pairs) {
+				did_something = true;
+				log_debug("  Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name);
+
+				for (auto &[port, sig] : cell->connections()) {
+					if (cell->output(port)) {
+						module->connect(sig, other_cell->getPort(port));
+					}
+				}
+
+				log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
+				module->remove(cell);
+				total_count++;
+				iter_count++;
+			}
+			log("removed %d cells\n", iter_count);
+
+
+				// hashes[cell] = hash;
+
+				// auto [found, inserted] = first_with_hash.emplace(hash, cell);
+
+				// if (inserted) {
+				// 	hashes.emplace(cell, hash);
+				// 	continue;
+				// }
+
+
+				// // if (check_candidate(found->second))
+				// // 	continue;
+
+				// auto found_more = more_with_hash[hash];
+
+				// // for (auto other_cell : found_more) {
+				// // 	if (check_candidate(other_cell))
+				// // 		continue;
+				// // }
+
+				// found_more.emplace(cell);
+				// hashes.emplace(cell, hash);
+
+				// // if (compare_cell_parameters_and_connections(found->second, cell)) {
+
+				// // }
+
+
+				// auto check_candidate = [&](Cell *other_cell) -> bool {
+				// 	if (!compare_cell_parameters_and_connections(other_cell, cell))
+				// 		return false;
+
+				// 	if (cell->has_keep_attr())
+				// 		if (other_cell->has_keep_attr())
+				// 			return false;
+
+				// 	forget_cell(cell);
+
+
+
+				// 	return true;
+
+				// };
+
+				// if (!check_candidate(found->second)) {
+				// }
+
+
+			// for ()
+
+
+				// auto [cell_in_map, inserted] = known_cells.insert(cell);
+				// if (!inserted) {
+				// 	// We've failed to insert since we already have an equivalent cell
+				// 	Cell* other_cell = *cell_in_map;
+				// 	if (cell->has_keep_attr()) {
+				// 		if (other_cell->has_keep_attr())
+				// 			continue;
+				// 		known_cells.erase(other_cell);
+				// 		known_cells.insert(cell);
+				// 		std::swap(other_cell, cell);
+				// 	}
+
+				// 	did_something = true;
+				// 	log_debug("  Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name);
+				// 	for (auto &it : cell->connections()) {
+				// 		if (cell->output(it.first)) {
+				// 			RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
+				// 			log_debug("    Redirecting output %s: %s = %s\n", it.first,
+				// 					log_signal(it.second), log_signal(other_sig));
+				// 			Const init = initvals(other_sig);
+				// 			initvals.remove_init(it.second);
+				// 			initvals.remove_init(other_sig);
+				// 			module->connect(RTLIL::SigSig(it.second, other_sig));
+				// 			assign_map.add(it.second, other_sig);
+				// 			initvals.set_init(other_sig, init);
+				// 		}
+				// 	}
+				// 	log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
+				// 	module->remove(cell);
+				// 	total_count++;
+				// }
+
+		}
+
+		log_suppressed();
+	}
+};
+
+struct OptMergeIncPass : public Pass {
+	OptMergeIncPass() : Pass("opt_merge", "consolidate identical cells") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    opt_merge_inc [options] [selection]\n");
+		log("\n");
+		log("This pass identifies cells with identical type and input signals. Such cells\n");
+		log("are then merged to one cell.\n");
+		log("\n");
+		log("    -nomux\n");
+		log("        Do not merge MUX cells.\n");
+		log("\n");
+		log("    -share_all\n");
+		log("        Operate on all cell types, not just built-in types.\n");
+		log("\n");
+		log("    -keepdc\n");
+		log("        Do not merge flipflops with don't-care bits in their initial value.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing OPT_MERGE_INC pass (detect identical cells).\n");
+
+		bool mode_nomux = false;
+		bool mode_share_all = false;
+		bool mode_keepdc = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-nomux") {
+				mode_nomux = true;
+				continue;
+			}
+			if (arg == "-share_all") {
+				mode_share_all = true;
+				continue;
+			}
+			if (arg == "-keepdc") {
+				mode_keepdc = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		design->sigNormalize(true);
+
+		int total_count = 0;
+		for (auto module : design->selected_modules()) {
+			OptMergeIncWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc);
+			total_count += worker.total_count;
+		}
+
+
+		// design->sigNormalize(false);
+
+		if (total_count)
+			design->scratchpad_set_bool("opt.did_something", true);
+		log("Removed a total of %d cells.\n", total_count);
+	}
+} OptMergeIncPass;
+
+PRIVATE_NAMESPACE_END

passes/techmap/bufnorm.cc

@@ -94,8 +94,11 @@ struct BufnormPass : public Pass {
 		log("    -update\n");
 		log("        Enter 'buffered-normalized mode' and (re-)normalize.\n");
 		log("\n");
+		log("    -signorm\n");
+		log("        Enter 'signal-normalized mode' and (re-)normalize.\n");
+		log("\n");
 		log("    -reset\n");
-		log("        Leave 'buffered-normalized mode' without changing the netlist.\n");
+		log("        Leave '{buffered,signal}-normalized mode' without changing the netlist.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -116,6 +119,7 @@ struct BufnormPass : public Pass {
 		bool conn_mode = false;
 
 		bool update_mode = false;
+		bool signorm_mode = false;
 		bool reset_mode = false;
 		bool got_non_update_reset_opt = false;
 
@@ -198,6 +202,10 @@ struct BufnormPass : public Pass {
 				update_mode = true;
 				continue;
 			}
+			if (arg == "-signorm") {
+				signorm_mode = true;
+				continue;
+			}
 			if (arg == "-reset") {
 				reset_mode = true;
 				continue;
@@ -221,6 +229,9 @@ struct BufnormPass : public Pass {
 		if (update_mode && got_non_update_reset_opt)
 			log_cmd_error("Option -update can't be mixed with other options.\n");
 
+		if (signorm_mode && got_non_update_reset_opt)
+			log_cmd_error("Option -signorm can't be mixed with other options.\n");
+
 		if (reset_mode && got_non_update_reset_opt)
 			log_cmd_error("Option -reset can't be mixed with other options.\n");
 
@@ -229,8 +240,14 @@ struct BufnormPass : public Pass {
 			return;
 		}
 
+		if (signorm_mode) {
+			design->sigNormalize();
+			return;
+		}
+
 		if (reset_mode) {
 			design->bufNormalize(false);
+			design->sigNormalize(false);
 			return;
 		}