WIP half broken snapshot

kernel/rtlil.h

@@ -122,8 +122,11 @@ namespace RTLIL
 	struct Binding;
 	struct IdString;
 	struct OwningIdString;
+	struct StaticIdString;
+	struct SigNormIndex;
 
 	typedef std::pair<SigSpec, SigSpec> SigSig;
+	struct PortBit;
 };
 
 struct RTLIL::IdString
@@ -1892,7 +1895,9 @@ struct RTLIL::Design
 	dict<std::string, std::string> scratchpad;
 
 	bool flagBufferedNormalized = false;
+	bool flagSigNormalized = false;
 	void bufNormalize(bool enable=true);
+	void sigNormalize(bool enable=true);
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
@@ -2053,6 +2058,10 @@ struct RTLIL::Design
 
 struct RTLIL::Module : public RTLIL::NamedObject
 {
+	friend struct RTLIL::SigNormIndex;
+	friend struct RTLIL::Cell;
+	friend struct RTLIL::Design;
+
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
 
@@ -2111,6 +2120,18 @@ public:
 	dict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;
 	void bufNormalize();
 
+protected:
+	SigNormIndex *sig_norm_index = nullptr;
+	void clear_sig_norm_index();
+	int timestamp_ = 0;
+public:
+	void sigNormalize();
+
+	int timestamp() const { return timestamp_; }
+	int next_timestamp();
+	std::vector<Cell *> dirty_cells(int starting_from);
+	const pool<PortBit> &fanout(SigBit bit);
+
 	template<typename T> void rewrite_sigspecs(T &functor);
 	template<typename T> void rewrite_sigspecs2(T &functor);
 	void cloneInto(RTLIL::Module *new_mod) const;
@@ -2430,6 +2451,7 @@ struct RTLIL::Wire : public RTLIL::NamedObject
 protected:
 	// use module->addWire() and module->remove() to create or destroy wires
 	friend struct RTLIL::Module;
+	friend struct RTLIL::SigNormIndex;
 	Wire();
 	~Wire();
 
@@ -2627,6 +2649,33 @@ public:
 	std::string to_rtlil_str() const;
 };
 
+struct RTLIL::PortBit
+{
+	RTLIL::Cell *cell;
+	RTLIL::IdString port;
+	int offset;
+	PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
+
+	bool operator<(const PortBit &other) const {
+		if (cell != other.cell)
+			return cell < other.cell;
+		if (port != other.port)
+			return port < other.port;
+		return offset < other.offset;
+	}
+
+	bool operator==(const PortBit &other) const {
+		return cell == other.cell && port == other.port && offset == other.offset;
+	}
+
+	[[nodiscard]] Hasher hash_into(Hasher h) const {
+		h.eat(cell->name);
+		h.eat(port);
+		h.eat(offset);
+		return h;
+	}
+};
+
 
 inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }