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remove invalid tests
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4 changed files with 21 additions and 65 deletions
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@ -14,7 +14,7 @@ module test(
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reg [7:0] mem[3:254];
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assign rd[7:0] = mem[{ra, 1'b0}];
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assign rd[15:0] = mem[{ra, 1'b1}];
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assign rd[15:8] = mem[{ra, 1'b1}];
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initial begin
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mem[5] = 8'h12;
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