mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 03:45:52 +00:00
Code Activity

start modify files to reflect cyclone iv LE - architecture

Browse source
This commit is contained in:
Artur Swiderski 2020-10-15 23:31:16 +02:00
parent 8021773072
commit 41f83c19fd
3 changed files with 32 additions and 58 deletions
Download patch file Download diff file Expand all files Collapse all files

32
techlibs/intel_le/common/le_sim.v
View file

@ -231,11 +231,10 @@ assign Q = ~A;
endmodule
(* abc9_box, lib_whitebox *)
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output , (* abc9_carry *) output CO);
parameter LUT = 16'h0000;
parameter sum_lutc_input = "cin";
`ifdef cycloneiv
specify
(A => SO) = 1342;
@ -253,30 +252,15 @@ specify
(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify
`endif
`ifdef cyclone10gx
specify
(A => SO) = 644;
(B => SO) = 477;
(C => SO) = 416;
(D0 => SO) = 380;
(D1 => SO) = 431;
(CI => SO) = 276;
(A => CO) = 525;
(B => CO) = 433;
(C => CO) = 712;
(D0 => CO) = 653;
(D1 => CO) = 593;
(CI => CO) = 16;
endspecify
`endif
wire q0, q1;
assign q0 = LUT0 >> {D0, C, B, A};
assign q1 = LUT1 >> {D1, C, B, A};
assign q0 = LUT0 >> sum_lutc_input == "cin" : {D, CI, B, A},{D, C, B, A};
assign q1 = LUT0 >> sum_lutc_input == "cin" : {'b0, CI, B, A},{'b0, C, B, A};
assign {CO, SO} = q0 + !q1 + CI;
assign SO = D ? q1 : q0;
assign CO = q0;
endmodule