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Add or-assignment operator

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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-03 13:51:57 +02:00
parent 0835a86e30
commit 416a66aee8
2 changed files with 11 additions and 1 deletions
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10
frontends/verilog/verilog_parser.y
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@ -259,7 +259,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC
%token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
@ -2334,6 +2334,14 @@ simple_behavioral_stmt:
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
} |
attr lvalue TOK_OR_ASSIGN delay expr {
AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
SET_AST_NODE_LOC(or_node, @2, @5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
};
// this production creates the obligatory if-else shift/reduce conflict