From 87717d67d1bf24e0fa120a16dda71a47b33fa347 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jun 2020 11:56:43 +0200
Subject: [PATCH 1/3] expose pass fix
---
passes/sat/expose.cc | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 5fe7efc34..e115b184e 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -445,6 +445,8 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
+ std::map<RTLIL::Wire*, RTLIL::IdString> wire_map;
+
for (auto w : module->wires())
{
if (flag_shared) {
@@ -462,8 +464,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
- RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
- out_to_in_map.add(w, in_wire);
+ wire_map[w] = NEW_ID;
}
}
else
@@ -474,12 +475,22 @@ struct ExposePass : public Pass {
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
- in_wire->port_input = true;
- out_to_in_map.add(sigmap(w), in_wire);
+ wire_map[w] = w->name.str() + sep + "i";
}
}
}
+ for (auto &wm : wire_map)
+ {
+ if (flag_input) {
+ RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
+ out_to_in_map.add(wm.first, in_wire);
+ }
+ if (flag_cut) {
+ RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
+ in_wire->port_input = true;
+ out_to_in_map.add(sigmap(wm.first), in_wire);
+ }
+ }
if (flag_input)
{
From 0545a042f363efe1c1543d2b85269efe394c830f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jun 2020 14:42:48 +0200
Subject: [PATCH 2/3] cleanup
---
passes/sat/expose.cc | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index e115b184e..20b8536fc 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -479,21 +479,15 @@ struct ExposePass : public Pass {
}
}
}
- for (auto &wm : wire_map)
- {
- if (flag_input) {
- RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
- out_to_in_map.add(wm.first, in_wire);
- }
- if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
- in_wire->port_input = true;
- out_to_in_map.add(sigmap(wm.first), in_wire);
- }
- }
if (flag_input)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
+ out_to_in_map.add(wm.first, in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
@@ -508,6 +502,13 @@ struct ExposePass : public Pass {
if (flag_cut)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
+ in_wire->port_input = true;
+ out_to_in_map.add(sigmap(wm.first), in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
From 405b4e97a1302340e648b06cc8a1bb11e34db806 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jun 2020 14:45:49 +0200
Subject: [PATCH 3/3] Give error that options are exclusive
---
passes/sat/expose.cc | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 20b8536fc..2c65821cf 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -281,11 +281,15 @@ struct ExposePass : public Pass {
flag_dff = true;
continue;
}
- if (args[argidx] == "-cut" && !flag_input) {
+ if (args[argidx] == "-cut") {
+ if (flag_input)
+ log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_cut = true;
continue;
}
- if (args[argidx] == "-input" && !flag_cut) {
+ if (args[argidx] == "-input") {
+ if (flag_cut)
+ log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_input = true;
continue;
}