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Different approach to timing
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Eddie Hung
parent
c83a667555
commit
41256f48a5
4 changed files with 198 additions and 408 deletions
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@ -44,48 +44,6 @@ endmodule
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module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
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endmodule
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// Boxes used to represent the comb/seq behaviour of DSP48E1
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// With abc_map.v responsible for disconnecting inputs to
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// the combinatorial DSP48E1 model by a register (e.g.
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// disconnecting A when AREG, MREG or PREG is enabled)
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// this blackbox captures the existence of a replacement
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// path between AREG/BREG/CREG/etc. and P/PCOUT.
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// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
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// the box at zero time, the combinatorial delay through
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// these boxes thus represents the clock-to-q delay
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// (arrival time) at P/PCOUT.
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// Doing so should means that ABC is able to analyse the
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// worst-case delay through to P, regardless of if it was
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// through any combinatorial paths (e.g. B, below) or an
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// internal register (A2REG).
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// However, the true value of being as complete as this is
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// questionable since if AREG=1 and BREG=0 (as below)
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// then the worse-case path would very likely be through B
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// and very unlikely to be through AREG.Q...?
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//
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// In graphical form:
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//
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// NEW "PI" >>---+
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// for AREG.Q |
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// |
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// +---------+ | __
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// A >>--X X-| | +--| \
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// | DSP48E1 |P | |--->> P
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// | AREG=1 |-------|__/
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// B >>------| |
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// +---------+
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//
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`define ABC_DSP48E1_MUX(__NAME__) """
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module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
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endmodule
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"""
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(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
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(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
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(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
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(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
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(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
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(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
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`define ABC_DSP48E1(__NAME__) """
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module \$__ABC_DSP48E1_MULT (
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output [29:0] ACOUT,
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@ -173,3 +131,66 @@ endmodule
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(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
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(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
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(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
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// Modules used to model the comb/seq behaviour of DSP48E1
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// With abc_map.v responsible for splicing the below modules
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// into between the combinatorial DSP48E1 box (e.g. disconnecting
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// A when AREG, MREG or PREG is enabled and splicing in the
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// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram
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// below) this acts to first disables the combinatorial path
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// (as there is no connectivity through REG), and secondly,
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// since this is blackbox a new PI will be introduced, one which
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// will have the relevant arrival time (corresponding to delay from
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// AREG to P) attached.
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// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a
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// sequential nature, they are not passed as a box to ABC./
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//
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// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial
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// blackbox that is passed to ABC, with zero delay.
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//
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// Doing so should means that ABC is able to analyse the
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// worst-case delay through to P, regardless of if it was
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// through any combinatorial paths (e.g. B, below) or an
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// internal register (A2REG).
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// However, the true value of being as complete as this is
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// questionable since if AREG=1 and BREG=0 (as below)
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// then the worse-case path would very likely be through B
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// and very unlikely to be through AREG.Q...?
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//
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// In graphical form:
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//
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// +-----+
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// +-------| REG |-----+
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// | +-----+ |
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// | |
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// | +---------+ | __
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// A >>-+X X-| | +--| \
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// | DSP48E1 |P | M |--->> P
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// | AREG=1 |-------|__/
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// B >>------| |
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// +---------+
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//
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(* abc_box_id=2100 *)
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module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
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endmodule
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module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
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module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
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