mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-02 12:37:53 +00:00
Code Activity

test suite

Browse source
This commit is contained in:
Lofty 2025-09-24 20:56:27 +01:00
parent 58701cb380
commit 40dbea0235
38 changed files with 1282 additions and 161 deletions
Download patch file Download diff file Expand all files Collapse all files

32
tests/arch/analogdevices/macc.ys Normal file
View file

@ -0,0 +1,32 @@
read_verilog macc.v
design -save read
hierarchy -top macc
proc
#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FFRE t:DSP48E1 %% t:* %D
design -load read
hierarchy -top macc2
proc
#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc2 # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 1 t:FFRE
select -assert-count 1 t:LUT2
select -assert-count 40 t:LUT3
select -assert-none t:BUFG t:DSP48E1 t:FFRE t:LUT2 t:LUT3 %% t:* %D