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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 58701cb380
commit 40dbea0235
38 changed files with 1282 additions and 161 deletions
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tests/arch/analogdevices/lutram.ys Normal file
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design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 8 t:FFRE
select -assert-count 1 t:RAM32M
select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
dump
select -assert-count 1 t:BUFG
select -assert-count 8 t:FFRE
select -assert-count 8 t:RAM64X1S
select -assert-none t:BUFG t:FFRE t:RAM64X1S %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w3r
select -assert-count 1 t:BUFG
select -assert-count 24 t:FFRE
select -assert-count 4 t:RAM32M
select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r -chparam A_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w3r
select -assert-count 1 t:BUFG
select -assert-count 24 t:FFRE
select -assert-count 16 t:RAM64X1D
select -assert-none t:BUFG t:FFRE t:RAM64X1D %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FFRE
select -assert-count 1 t:RAM32M
select -assert-none t:BUFG t:FFRE t:RAM32M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FFRE
select -assert-count 6 t:RAM64X1S
select -assert-none t:BUFG t:FFRE t:RAM64X1S %% t:* %D