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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 58701cb380
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tests/arch/analogdevices/fsm.ys Normal file
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read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
design -save orig
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FFRE
select -assert-count 1 t:INV
select -assert-count 1 t:LUT3
select -assert-count 1 t:LUT4
select -assert-count 5 t:LUT5
select -assert-none t:BUFG t:FFRE t:INV t:LUT3 t:LUT4 t:LUT5 %% t:* %D