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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 58701cb380
commit 40dbea0235
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tests/arch/analogdevices/bug1462.ys Normal file
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read_verilog << EOF
module top(...);
input wire [31:0] A;
output wire [31:0] P;
assign P = A * 32'h12300000;
endmodule
EOF
synth_analogdevices