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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 58701cb380
commit 40dbea0235
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tests/arch/analogdevices/add_sub.ys Normal file
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read_verilog ../common/add_sub.v
hierarchy -top top
proc
design -save orig
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:LUT2
select -assert-count 2 t:CRY4
select -assert-none t:LUT2 t:CRY4 %% t:* %D