mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 20:50:51 +00:00
Code Activity

Docs: Reflow line length

Browse source
This commit is contained in:
Krystine Sherwin 2024-05-03 13:38:01 +12:00
parent 829e02ec5b
commit 40ba92e956
No known key found for this signature in database
20 changed files with 782 additions and 785 deletions
Download patch file Download diff file Expand all files Collapse all files

8
docs/source/yosys_internals/techmap.rst
View file

@ -1,8 +1,8 @@
Techmap by example
------------------
As a quick recap, the `techmap` command replaces cells in the design
with implementations given as Verilog code (called "map files"). It can replace
As a quick recap, the `techmap` command replaces cells in the design with
implementations given as Verilog code (called "map files"). It can replace
Yosys' internal cell types (such as `$or`) as well as user-defined cell types.
- Verilog parameters are used extensively to customize the internal cell types.
@ -94,8 +94,8 @@ Scripting in map modules
.. note:: PROTIP:
Commands such as `shell`, ``show -pause``, and `dump` can
be used in the ``_TECHMAP_DO_*`` scripts for debugging map modules.
Commands such as `shell`, ``show -pause``, and `dump` can be used in the
``_TECHMAP_DO_*`` scripts for debugging map modules.
Example: