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Docs: Reflow line length
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Krystine Sherwin
parent
829e02ec5b
commit
40ba92e956
20 changed files with 782 additions and 785 deletions
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@ -73,16 +73,16 @@ also have the following parameters:
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:verilog:`Y = !A` $logic_not
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================== ============
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For the unary cells that output a logical value (`$reduce_and`,
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`$reduce_or`, `$reduce_xor`, `$reduce_xnor`, `$reduce_bool`,
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`$logic_not`), when the ``\Y_WIDTH`` parameter is greater than 1, the output
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is zero-extended, and only the least significant bit varies.
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For the unary cells that output a logical value (`$reduce_and`, `$reduce_or`,
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`$reduce_xor`, `$reduce_xnor`, `$reduce_bool`, `$logic_not`), when the
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``\Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and only
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the least significant bit varies.
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Note that `$reduce_or` and `$reduce_bool` actually represent the same logic
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function. But the HDL frontends generate them in different situations. A
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`$reduce_or` cell is generated when the prefix ``|`` operator is being used. A
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`$reduce_bool` cell is generated when a bit vector is used as a condition in
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an ``if``-statement or ``?:``-expression.
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`$reduce_bool` cell is generated when a bit vector is used as a condition in an
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``if``-statement or ``?:``-expression.
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Binary operators
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~~~~~~~~~~~~~~~~
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@ -91,15 +91,15 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
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``\Y``. They also have the following parameters:
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``\A_SIGNED``
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Set to a non-zero value if the input ``\A`` is signed and therefore
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should be sign-extended when needed.
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Set to a non-zero value if the input ``\A`` is signed and therefore should be
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sign-extended when needed.
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``\A_WIDTH``
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The width of the input port ``\A``.
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``\B_SIGNED``
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Set to a non-zero value if the input ``\B`` is signed and therefore
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should be sign-extended when needed.
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Set to a non-zero value if the input ``\B`` is signed and therefore should be
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sign-extended when needed.
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``\B_WIDTH``
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The width of the input port ``\B``.
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@ -130,29 +130,28 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
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:verilog:`Y = A ** B` $pow ``N/A`` $modfloor
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======================= ============= ======================= =========
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The `$shl` and `$shr` cells implement logical shifts, whereas the `$sshl`
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and `$sshr` cells implement arithmetic shifts. The `$shl` and `$sshl`
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cells implement the same operation. All four of these cells interpret the second
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The `$shl` and `$shr` cells implement logical shifts, whereas the `$sshl` and
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`$sshr` cells implement arithmetic shifts. The `$shl` and `$sshl` cells
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implement the same operation. All four of these cells interpret the second
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operand as unsigned, and require ``\B_SIGNED`` to be zero.
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Two additional shift operator cells are available that do not directly
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correspond to any operator in Verilog, `$shift` and `$shiftx`. The
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`$shift` cell performs a right logical shift if the second operand is positive
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(or unsigned), and a left logical shift if it is negative. The `$shiftx` cell
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performs the same operation as the `$shift` cell, but the vacated bit
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positions are filled with undef (x) bits, and corresponds to the Verilog indexed
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part-select expression.
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correspond to any operator in Verilog, `$shift` and `$shiftx`. The `$shift` cell
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performs a right logical shift if the second operand is positive (or unsigned),
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and a left logical shift if it is negative. The `$shiftx` cell performs the same
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operation as the `$shift` cell, but the vacated bit positions are filled with
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undef (x) bits, and corresponds to the Verilog indexed part-select expression.
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For the binary cells that output a logical value (`$logic_and`, `$logic_or`,
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`$eqx`, `$nex`, `$lt`, `$le`, `$eq`, `$ne`, `$ge`, `$gt`), when
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the ``\Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and
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only the least significant bit varies.
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`$eqx`, `$nex`, `$lt`, `$le`, `$eq`, `$ne`, `$ge`, `$gt`), when the ``\Y_WIDTH``
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parameter is greater than 1, the output is zero-extended, and only the least
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significant bit varies.
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Division and modulo cells are available in two rounding modes. The original
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`$div` and `$mod` cells are based on truncating division, and correspond to
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the semantics of the verilog ``/`` and ``%`` operators. The `$divfloor` and
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`$modfloor` cells represent flooring division and flooring modulo, the latter
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of which is also known as "remainder" in several languages. See
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`$div` and `$mod` cells are based on truncating division, and correspond to the
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semantics of the verilog ``/`` and ``%`` operators. The `$divfloor` and
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`$modfloor` cells represent flooring division and flooring modulo, the latter of
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which is also known as "remainder" in several languages. See
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:numref:`tab:CellLib_divmod` for a side-by-side comparison between the different
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semantics.
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@ -187,9 +186,9 @@ all of the specified width. This cell also has a single bit control input
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it is 1 the value from the ``\B`` input is sent to the output. So the `$mux`
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cell implements the function :verilog:`Y = S ? B : A`.
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The `$pmux` cell is used to multiplex between many inputs using a one-hot
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select signal. Cells of this type have a ``\WIDTH`` and a ``\S_WIDTH`` parameter
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and inputs ``\A``, ``\B``, and ``\S`` and an output ``\Y``. The ``\S`` input is
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The `$pmux` cell is used to multiplex between many inputs using a one-hot select
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signal. Cells of this type have a ``\WIDTH`` and a ``\S_WIDTH`` parameter and
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inputs ``\A``, ``\B``, and ``\S`` and an output ``\Y``. The ``\S`` input is
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``\S_WIDTH`` bits wide. The ``\A`` input and the output are both ``\WIDTH`` bits
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wide and the ``\B`` input is ``\WIDTH*\S_WIDTH`` bits wide. When all bits of
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``\S`` are zero, the value from ``\A`` input is sent to the output. If the
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@ -199,8 +198,8 @@ from ``\S`` is set the output is undefined. Cells of this type are used to model
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"parallel cases" (defined by using the ``parallel_case`` attribute or detected
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by an optimization).
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The `$tribuf` cell is used to implement tristate logic. Cells of this type
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have a ``\WIDTH`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The
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The `$tribuf` cell is used to implement tristate logic. Cells of this type have
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a ``\WIDTH`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The
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``\A`` input and ``\Y`` output are ``\WIDTH`` bits wide, and the ``\EN`` input
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is one bit wide. When ``\EN`` is 0, the output is not driven. When ``\EN`` is 1,
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the value from ``\A`` input is sent to the ``\Y`` output. Therefore, the
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@ -224,27 +223,27 @@ parameters:
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The width of inputs ``\SET`` and ``\CLR`` and output ``\Q``.
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``\SET_POLARITY``
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The set input bits are active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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The set input bits are active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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``\CLR_POLARITY``
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The reset input bits are active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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The reset input bits are active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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Both set and reset inputs have separate bits for every output bit. When both the
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set and reset inputs of an `$sr` cell are active for a given bit index, the
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reset input takes precedence.
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D-type flip-flops are represented by `$dff` cells. These cells have a clock
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port ``\CLK``, an input port ``\D`` and an output port ``\Q``. The following
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D-type flip-flops are represented by `$dff` cells. These cells have a clock port
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``\CLK``, an input port ``\D`` and an output port ``\Q``. The following
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parameters are available for `$dff` cells:
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``\WIDTH``
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The width of input ``\D`` and output ``\Q``.
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``\CLK_POLARITY``
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Clock is active on the positive edge if this parameter has the value
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``1'b1`` and on the negative edge if this parameter is ``1'b0``.
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Clock is active on the positive edge if this parameter has the value ``1'b1``
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and on the negative edge if this parameter is ``1'b0``.
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D-type flip-flops with asynchronous reset are represented by `$adff` cells. As
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the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
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@ -258,8 +257,8 @@ additional two parameters:
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``\ARST_VALUE``
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The state of ``\Q`` will be set to this value when the reset is active.
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Usually these cells are generated by the `proc` pass using the
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information in the designs RTLIL::Process objects.
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Usually these cells are generated by the `proc` pass using the information in
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the designs RTLIL::Process objects.
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D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
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the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
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@ -267,14 +266,14 @@ also have a single-bit ``\SRST`` input port for the reset pin and the following
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additional two parameters:
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``\SRST_POLARITY``
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The synchronous reset is active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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The synchronous reset is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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``\SRST_VALUE``
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The state of ``\Q`` will be set to this value when the reset is active.
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Note that the `$adff` and `$sdff` cells can only be used when the reset
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value is constant.
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Note that the `$adff` and `$sdff` cells can only be used when the reset value is
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constant.
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D-type flip-flops with asynchronous load are represented by `$aldff` cells. As
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the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
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@ -283,25 +282,24 @@ also have a single-bit ``\ALOAD`` input port for the async load enable pin, a
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following additional parameter:
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``\ALOAD_POLARITY``
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The asynchronous load is active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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The asynchronous load is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
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cells. As the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In
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addition they also have multi-bit ``\SET`` and ``\CLR`` input ports and the
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corresponding polarity parameters, like `$sr` cells.
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D-type flip-flops with enable are represented by `$dffe`, `$adffe`,
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`$aldffe`, `$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced
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variants of `$dff`, `$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset
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over enable) and `$sdff` (with enable over reset) cells, respectively. They
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have the same ports and parameters as their base cell. In addition they also
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have a single-bit ``\EN`` input port for the enable pin and the following
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parameter:
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D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`,
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`$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`,
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`$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset over enable) and `$sdff` (with
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enable over reset) cells, respectively. They have the same ports and parameters
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as their base cell. In addition they also have a single-bit ``\EN`` input port
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for the enable pin and the following parameter:
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``\EN_POLARITY``
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The enable input is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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The enable input is active-high if this parameter has the value ``1'b1`` and
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active-low if this parameter is ``1'b0``.
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D-type latches are represented by `$dlatch` cells. These cells have an enable
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port ``\EN``, an input port ``\D``, and an output port ``\Q``. The following
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@ -311,14 +309,14 @@ parameters are available for `$dlatch` cells:
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The width of input ``\D`` and output ``\Q``.
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``\EN_POLARITY``
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The enable input is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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The enable input is active-high if this parameter has the value ``1'b1`` and
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active-low if this parameter is ``1'b0``.
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The latch is transparent when the ``\EN`` input is active.
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D-type latches with reset are represented by `$adlatch` cells. In addition to
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`$dlatch` ports and parameters, they also have a single-bit ``\ARST`` input
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port for the reset pin and the following additional parameters:
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`$dlatch` ports and parameters, they also have a single-bit ``\ARST`` input port
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for the reset pin and the following additional parameters:
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``\ARST_POLARITY``
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The asynchronous reset is active-high if this parameter has the value
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@ -363,56 +361,53 @@ parameters:
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The number of address bits (width of the ``\ADDR`` input port).
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``\WIDTH``
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The number of data bits (width of the ``\DATA`` output port). Note that
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this may be a power-of-two multiple of the underlying memory's width --
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such ports are called wide ports and access an aligned group of cells at
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once. In this case, the corresponding low bits of ``\ADDR`` must be
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tied to 0.
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The number of data bits (width of the ``\DATA`` output port). Note that this
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may be a power-of-two multiple of the underlying memory's width -- such ports
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are called wide ports and access an aligned group of cells at once. In this
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case, the corresponding low bits of ``\ADDR`` must be tied to 0.
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``\CLK_ENABLE``
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When this parameter is non-zero, the clock is used. Otherwise this read
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port is asynchronous and the ``\CLK`` input is not used.
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When this parameter is non-zero, the clock is used. Otherwise this read port
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is asynchronous and the ``\CLK`` input is not used.
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``\CLK_POLARITY``
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Clock is active on the positive edge if this parameter has the value
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``1'b1`` and on the negative edge if this parameter is ``1'b0``.
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Clock is active on the positive edge if this parameter has the value ``1'b1``
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and on the negative edge if this parameter is ``1'b0``.
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``\TRANSPARENCY_MASK``
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This parameter is a bitmask of write ports that this read port is
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transparent with. The bits of this parameter are indexed by the write
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port's ``\PORTID`` parameter. Transparency can only be enabled between
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synchronous ports sharing a clock domain. When transparency is enabled
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for a given port pair, a read and write to the same address in the same
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cycle will return the new value. Otherwise the old value is returned.
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This parameter is a bitmask of write ports that this read port is transparent
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with. The bits of this parameter are indexed by the write port's ``\PORTID``
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parameter. Transparency can only be enabled between synchronous ports sharing
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a clock domain. When transparency is enabled for a given port pair, a read
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and write to the same address in the same cycle will return the new value.
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Otherwise the old value is returned.
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``\COLLISION_X_MASK``
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This parameter is a bitmask of write ports that have undefined collision
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behavior with this port. The bits of this parameter are indexed by the
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write port's ``\PORTID`` parameter. This behavior can only be enabled
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between synchronous ports sharing a clock domain. When undefined
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collision is enabled for a given port pair, a read and write to the same
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address in the same cycle will return the undefined (all-X) value.This
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option is exclusive (for a given port pair) with the transparency
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option.
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behavior with this port. The bits of this parameter are indexed by the write
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port's ``\PORTID`` parameter. This behavior can only be enabled between
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synchronous ports sharing a clock domain. When undefined collision is enabled
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for a given port pair, a read and write to the same address in the same cycle
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will return the undefined (all-X) value.This option is exclusive (for a given
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port pair) with the transparency option.
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``\ARST_VALUE``
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Whenever the ``\ARST`` input is asserted, the data output will be reset
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to this value. Only used for synchronous ports.
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Whenever the ``\ARST`` input is asserted, the data output will be reset to
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this value. Only used for synchronous ports.
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``\SRST_VALUE``
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Whenever the ``\SRST`` input is synchronously asserted, the data output
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will be reset to this value. Only used for synchronous ports.
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Whenever the ``\SRST`` input is synchronously asserted, the data output will
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be reset to this value. Only used for synchronous ports.
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``\INIT_VALUE``
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The initial value of the data output, for synchronous ports.
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``\CE_OVER_SRST``
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If this parameter is non-zero, the ``\SRST`` input is only recognized
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when ``\EN`` is true. Otherwise, ``\SRST`` is recognized regardless of
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``\EN``.
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If this parameter is non-zero, the ``\SRST`` input is only recognized when
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``\EN`` is true. Otherwise, ``\SRST`` is recognized regardless of ``\EN``.
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The `$memwr_v2` cells have a clock input ``\CLK``, an enable input ``\EN``
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(one enable bit for each data bit), an address input ``\ADDR`` and a data input
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The `$memwr_v2` cells have a clock input ``\CLK``, an enable input ``\EN`` (one
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enable bit for each data bit), an address input ``\ADDR`` and a data input
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``\DATA``. They also have the following parameters:
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``\MEMID``
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@ -424,16 +419,16 @@ The `$memwr_v2` cells have a clock input ``\CLK``, an enable input ``\EN``
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``\WIDTH``
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The number of data bits (width of the ``\DATA`` output port). Like with
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`$memrd_v2` cells, the width is allowed to be any power-of-two
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multiple of memory width, with the corresponding restriction on address.
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`$memrd_v2` cells, the width is allowed to be any power-of-two multiple of
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memory width, with the corresponding restriction on address.
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``\CLK_ENABLE``
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When this parameter is non-zero, the clock is used. Otherwise this write
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port is asynchronous and the ``\CLK`` input is not used.
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When this parameter is non-zero, the clock is used. Otherwise this write port
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is asynchronous and the ``\CLK`` input is not used.
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``\CLK_POLARITY``
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Clock is active on positive edge if this parameter has the value
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``1'b1`` and on the negative edge if this parameter is ``1'b0``.
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Clock is active on positive edge if this parameter has the value ``1'b1`` and
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on the negative edge if this parameter is ``1'b0``.
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``\PORTID``
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An identifier for this write port, used to index write port bit mask
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|
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@ -442,16 +437,16 @@ The `$memwr_v2` cells have a clock input ``\CLK``, an enable input ``\EN``
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``\PRIORITY_MASK``
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This parameter is a bitmask of write ports that this write port has priority
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over in case of writing to the same address. The bits of this parameter are
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indexed by the other write port's ``\PORTID`` parameter. Write ports can
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only have priority over write ports with lower port ID. When two ports write
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to the same address and neither has priority over the other, the result is
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indexed by the other write port's ``\PORTID`` parameter. Write ports can only
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have priority over write ports with lower port ID. When two ports write to
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the same address and neither has priority over the other, the result is
|
||||
undefined. Priority can only be set between two synchronous ports sharing
|
||||
the same clock domain.
|
||||
|
||||
The `$meminit_v2` cells have an address input ``\ADDR``, a data input
|
||||
``\DATA``, with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter
|
||||
times ``\WORDS`` parameter, and a bit enable mask input ``\EN`` with width equal
|
||||
to ``\WIDTH`` parameter. All three of the inputs must resolve to a constant for
|
||||
The `$meminit_v2` cells have an address input ``\ADDR``, a data input ``\DATA``,
|
||||
with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter times
|
||||
``\WORDS`` parameter, and a bit enable mask input ``\EN`` with width equal to
|
||||
``\WIDTH`` parameter. All three of the inputs must resolve to a constant for
|
||||
synthesis to succeed.
|
||||
|
||||
``\MEMID``
|
||||
|
|
@ -472,19 +467,18 @@ synthesis to succeed.
|
|||
initialization conflict.
|
||||
|
||||
The HDL frontend models a memory using ``RTLIL::Memory`` objects and
|
||||
asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass
|
||||
(i.e. its various sub-passes) migrates `$dff` cells into the `$memrd_v2` and
|
||||
`$memwr_v2` cells making them synchronous, then converts them to a single
|
||||
`$mem_v2` cell and (optionally) maps this cell type to `$dff` cells for the
|
||||
individual words and multiplexer-based address decoders for the read and write
|
||||
interfaces. When the last step is disabled or not possible, a `$mem_v2` cell
|
||||
is left in the design.
|
||||
asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass (i.e. its
|
||||
various sub-passes) migrates `$dff` cells into the `$memrd_v2` and `$memwr_v2`
|
||||
cells making them synchronous, then converts them to a single `$mem_v2` cell and
|
||||
(optionally) maps this cell type to `$dff` cells for the individual words and
|
||||
multiplexer-based address decoders for the read and write interfaces. When the
|
||||
last step is disabled or not possible, a `$mem_v2` cell is left in the design.
|
||||
|
||||
The `$mem_v2` cell provides the following parameters:
|
||||
|
||||
``\MEMID``
|
||||
The name of the original ``RTLIL::Memory`` object that became this
|
||||
`$mem_v2` cell.
|
||||
The name of the original ``RTLIL::Memory`` object that became this `$mem_v2`
|
||||
cell.
|
||||
|
||||
``\SIZE``
|
||||
The number of words in the memory.
|
||||
|
|
@ -502,19 +496,19 @@ The `$mem_v2` cell provides the following parameters:
|
|||
The number of read ports on this memory cell.
|
||||
|
||||
``\RD_WIDE_CONTINUATION``
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a bitmask of
|
||||
"wide continuation" read ports. Such ports are used to represent the
|
||||
extra data bits of wide ports in the combined cell, and must have all
|
||||
control signals identical with the preceding port, except for address,
|
||||
which must have the proper sub-cell address encoded in the low bits.
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a bitmask of "wide
|
||||
continuation" read ports. Such ports are used to represent the extra data
|
||||
bits of wide ports in the combined cell, and must have all control signals
|
||||
identical with the preceding port, except for address, which must have the
|
||||
proper sub-cell address encoded in the low bits.
|
||||
|
||||
``\RD_CLK_ENABLE``
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a clock enable bit
|
||||
for each read port.
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a clock enable bit for
|
||||
each read port.
|
||||
|
||||
``\RD_CLK_POLARITY``
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a clock polarity
|
||||
bit for each read port.
|
||||
This parameter is ``\RD_PORTS`` bits wide, containing a clock polarity bit
|
||||
for each read port.
|
||||
|
||||
``\RD_TRANSPARENCY_MASK``
|
||||
This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a
|
||||
|
|
@ -523,62 +517,62 @@ The `$mem_v2` cell provides the following parameters:
|
|||
|
||||
``\RD_COLLISION_X_MASK``
|
||||
This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a
|
||||
concatenation of all ``\COLLISION_X_MASK`` values of the original
|
||||
`$memrd_v2` cells.
|
||||
concatenation of all ``\COLLISION_X_MASK`` values of the original `$memrd_v2`
|
||||
cells.
|
||||
|
||||
``\RD_CE_OVER_SRST``
|
||||
This parameter is ``\RD_PORTS`` bits wide, determining relative
|
||||
synchronous reset and enable priority for each read port.
|
||||
This parameter is ``\RD_PORTS`` bits wide, determining relative synchronous
|
||||
reset and enable priority for each read port.
|
||||
|
||||
``\RD_INIT_VALUE``
|
||||
This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the initial
|
||||
value for each synchronous read port.
|
||||
|
||||
``\RD_ARST_VALUE``
|
||||
This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the
|
||||
asynchronous reset value for each synchronous read port.
|
||||
This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the asynchronous
|
||||
reset value for each synchronous read port.
|
||||
|
||||
``\RD_SRST_VALUE``
|
||||
This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the
|
||||
synchronous reset value for each synchronous read port.
|
||||
This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the synchronous
|
||||
reset value for each synchronous read port.
|
||||
|
||||
``\WR_PORTS``
|
||||
The number of write ports on this memory cell.
|
||||
|
||||
``\WR_WIDE_CONTINUATION``
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a bitmask of
|
||||
"wide continuation" write ports.
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a bitmask of "wide
|
||||
continuation" write ports.
|
||||
|
||||
``\WR_CLK_ENABLE``
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a clock enable bit
|
||||
for each write port.
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a clock enable bit for
|
||||
each write port.
|
||||
|
||||
``\WR_CLK_POLARITY``
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a clock polarity
|
||||
bit for each write port.
|
||||
This parameter is ``\WR_PORTS`` bits wide, containing a clock polarity bit
|
||||
for each write port.
|
||||
|
||||
``\WR_PRIORITY_MASK``
|
||||
This parameter is ``\WR_PORTS*\WR_PORTS`` bits wide, containing a
|
||||
concatenation of all ``\PRIORITY_MASK`` values of the original
|
||||
`$memwr_v2` cells.
|
||||
concatenation of all ``\PRIORITY_MASK`` values of the original `$memwr_v2`
|
||||
cells.
|
||||
|
||||
The `$mem_v2` cell has the following ports:
|
||||
|
||||
``\RD_CLK``
|
||||
This input is ``\RD_PORTS`` bits wide, containing all clock signals for
|
||||
the read ports.
|
||||
This input is ``\RD_PORTS`` bits wide, containing all clock signals for the
|
||||
read ports.
|
||||
|
||||
``\RD_EN``
|
||||
This input is ``\RD_PORTS`` bits wide, containing all enable signals for
|
||||
the read ports.
|
||||
This input is ``\RD_PORTS`` bits wide, containing all enable signals for the
|
||||
read ports.
|
||||
|
||||
``\RD_ADDR``
|
||||
This input is ``\RD_PORTS*\ABITS`` bits wide, containing all address
|
||||
signals for the read ports.
|
||||
This input is ``\RD_PORTS*\ABITS`` bits wide, containing all address signals
|
||||
for the read ports.
|
||||
|
||||
``\RD_DATA``
|
||||
This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data
|
||||
signals for the read ports.
|
||||
This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data signals
|
||||
for the read ports.
|
||||
|
||||
``\RD_ARST``
|
||||
This input is ``\RD_PORTS`` bits wide, containing all asynchronous reset
|
||||
|
|
@ -593,26 +587,25 @@ The `$mem_v2` cell has the following ports:
|
|||
the write ports.
|
||||
|
||||
``\WR_EN``
|
||||
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all enable
|
||||
signals for the write ports.
|
||||
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all enable signals
|
||||
for the write ports.
|
||||
|
||||
``\WR_ADDR``
|
||||
This input is ``\WR_PORTS*\ABITS`` bits wide, containing all address
|
||||
signals for the write ports.
|
||||
This input is ``\WR_PORTS*\ABITS`` bits wide, containing all address signals
|
||||
for the write ports.
|
||||
|
||||
``\WR_DATA``
|
||||
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
|
||||
signals for the write ports.
|
||||
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data signals for
|
||||
the write ports.
|
||||
|
||||
The `memory_collect` pass can be used to convert discrete
|
||||
`$memrd_v2`, `$memwr_v2`, and `$meminit_v2` cells belonging to the same
|
||||
memory to a single `$mem_v2` cell, whereas the `memory_unpack` pass
|
||||
performs the inverse operation. The `memory_dff` pass can combine
|
||||
asynchronous memory ports that are fed by or feeding registers into synchronous
|
||||
memory ports. The `memory_bram` pass can be used to recognize
|
||||
`$mem_v2` cells that can be implemented with a block RAM resource on an FPGA.
|
||||
The `memory_map` pass can be used to implement `$mem_v2` cells as
|
||||
basic logic: word-wide DFFs and address decoders.
|
||||
The `memory_collect` pass can be used to convert discrete `$memrd_v2`,
|
||||
`$memwr_v2`, and `$meminit_v2` cells belonging to the same memory to a single
|
||||
`$mem_v2` cell, whereas the `memory_unpack` pass performs the inverse operation.
|
||||
The `memory_dff` pass can combine asynchronous memory ports that are fed by or
|
||||
feeding registers into synchronous memory ports. The `memory_bram` pass can be
|
||||
used to recognize `$mem_v2` cells that can be implemented with a block RAM
|
||||
resource on an FPGA. The `memory_map` pass can be used to implement `$mem_v2`
|
||||
cells as basic logic: word-wide DFFs and address decoders.
|
||||
|
||||
Finite state machines
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -622,15 +615,17 @@ Add a brief description of the `$fsm` cell type.
|
|||
Coarse arithmetics
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The `$macc` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands.
|
||||
The `$macc` cell type represents a generalized multiply and accumulate
|
||||
operation. The cell is purely combinational. It outputs the result of summing up
|
||||
a sequence of products and other injected summands.
|
||||
|
||||
.. code-block::
|
||||
|
||||
Y = 0 +- a0factor1 * a0factor2 +- a1factor1 * a1factor2 +- ...
|
||||
+ B[0] + B[1] + ...
|
||||
|
||||
The A port consists of concatenated pairs of multiplier inputs ("factors").
|
||||
A zero length factor2 acts as a constant 1, turning factor1 into a simple summand.
|
||||
The A port consists of concatenated pairs of multiplier inputs ("factors"). A
|
||||
zero length factor2 acts as a constant 1, turning factor1 into a simple summand.
|
||||
|
||||
In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
|
||||
|
||||
|
|
@ -644,8 +639,8 @@ In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
|
|||
...
|
||||
};
|
||||
|
||||
The cell's ``CONFIG`` parameter determines the layout of cell port ``A``.
|
||||
The CONFIG parameter carries the following information:
|
||||
The cell's ``CONFIG`` parameter determines the layout of cell port ``A``. The
|
||||
CONFIG parameter carries the following information:
|
||||
|
||||
.. code-block::
|
||||
|
||||
|
|
@ -714,8 +709,8 @@ Formal verification cells
|
|||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Add information about `$check`, `$assert`, `$assume`, `$live`, `$fair`,
|
||||
`$cover`, `$equiv`, `$initstate`, `$anyconst`, `$anyseq`,
|
||||
`$anyinit`, `$allconst`, `$allseq` cells.
|
||||
`$cover`, `$equiv`, `$initstate`, `$anyconst`, `$anyseq`, `$anyinit`,
|
||||
`$allconst`, `$allseq` cells.
|
||||
|
||||
Add information about `$ff` and `$_FF_` cells.
|
||||
|
||||
|
|
@ -733,8 +728,8 @@ has the following parameters:
|
|||
The width (in bits) of the signal on the ``\ARGS`` port.
|
||||
|
||||
``\TRG_ENABLE``
|
||||
True if triggered on specific signals defined in ``\TRG``; false if
|
||||
triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1.
|
||||
True if triggered on specific signals defined in ``\TRG``; false if triggered
|
||||
whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1.
|
||||
|
||||
If ``\TRG_ENABLE`` is true, the following parameters also apply:
|
||||
|
||||
|
|
@ -792,12 +787,13 @@ width\ *?*
|
|||
(optional) The number of characters wide to pad to.
|
||||
|
||||
base
|
||||
* ``b`` for base-2 integers (binary)
|
||||
* ``o`` for base-8 integers (octal)
|
||||
* ``d`` for base-10 integers (decimal)
|
||||
* ``h`` for base-16 integers (hexadecimal)
|
||||
* ``c`` for ASCII characters/strings
|
||||
* ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`)
|
||||
* ``b`` for base-2 integers (binary)
|
||||
* ``o`` for base-8 integers (octal)
|
||||
* ``d`` for base-10 integers (decimal)
|
||||
* ``h`` for base-16 integers (hexadecimal)
|
||||
* ``c`` for ASCII characters/strings
|
||||
* ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and
|
||||
:verilog:`$realtime`)
|
||||
|
||||
For integers, this item may follow:
|
||||
|
||||
|
|
@ -1042,14 +1038,13 @@ Tables :numref:`%s <tab:CellLib_gates>`, :numref:`%s <tab:CellLib_gates_dffe>`,
|
|||
:numref:`%s <tab:CellLib_gates_adlatch>`, :numref:`%s
|
||||
<tab:CellLib_gates_dlatchsr>` and :numref:`%s <tab:CellLib_gates_sr>` list all
|
||||
cell types used for gate level logic. The cell types `$_BUF_`, `$_NOT_`,
|
||||
`$_AND_`, `$_NAND_`, `$_ANDNOT_`, `$_OR_`, `$_NOR_`, `$_ORNOT_`,
|
||||
`$_XOR_`, `$_XNOR_`, `$_AOI3_`, `$_OAI3_`, `$_AOI4_`, `$_OAI4_`,
|
||||
`$_MUX_`, `$_MUX4_`, `$_MUX8_`, `$_MUX16_` and `$_NMUX_` are used to
|
||||
model combinatorial logic. The cell type `$_TBUF_` is used to model tristate
|
||||
logic.
|
||||
`$_AND_`, `$_NAND_`, `$_ANDNOT_`, `$_OR_`, `$_NOR_`, `$_ORNOT_`, `$_XOR_`,
|
||||
`$_XNOR_`, `$_AOI3_`, `$_OAI3_`, `$_AOI4_`, `$_OAI4_`, `$_MUX_`, `$_MUX4_`,
|
||||
`$_MUX8_`, `$_MUX16_` and `$_NMUX_` are used to model combinatorial logic. The
|
||||
cell type `$_TBUF_` is used to model tristate logic.
|
||||
|
||||
The `$_MUX4_`, `$_MUX8_` and `$_MUX16_` cells are used to model wide
|
||||
muxes, and correspond to the following Verilog code:
|
||||
The `$_MUX4_`, `$_MUX8_` and `$_MUX16_` cells are used to model wide muxes, and
|
||||
correspond to the following Verilog code:
|
||||
|
||||
.. code-block:: verilog
|
||||
:force:
|
||||
|
|
@ -1114,8 +1109,8 @@ following Verilog code template:
|
|||
|
||||
The cell types ``$_DFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with
|
||||
asynchronous reset and enable. The values in the table for these cell types
|
||||
relate to the following Verilog code template, where ``RST_EDGE`` is
|
||||
``posedge`` if ``RST_LVL`` if ``1``, and ``negedge`` otherwise.
|
||||
relate to the following Verilog code template, where ``RST_EDGE`` is ``posedge``
|
||||
if ``RST_LVL`` if ``1``, and ``negedge`` otherwise.
|
||||
|
||||
.. code-block:: verilog
|
||||
:force:
|
||||
|
|
@ -1156,8 +1151,8 @@ in the table for these cell types relate to the following Verilog code template:
|
|||
The cell types ``$_DFFSR_[NP][NP][NP]_`` implement d-type flip-flops with
|
||||
asynchronous set and reset. The values in the table for these cell types relate
|
||||
to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` if
|
||||
``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge``
|
||||
if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
|
||||
``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge`` if
|
||||
``SET_LVL`` if ``1``, ``negedge`` otherwise.
|
||||
|
||||
.. code-block:: verilog
|
||||
:force:
|
||||
|
|
@ -1173,8 +1168,8 @@ if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
|
|||
The cell types ``$_DFFSRE_[NP][NP][NP][NP]_`` implement d-type flip-flops with
|
||||
asynchronous set and reset and enable. The values in the table for these cell
|
||||
types relate to the following Verilog code template, where ``RST_EDGE`` is
|
||||
``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE``
|
||||
is ``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
|
||||
``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is
|
||||
``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
|
||||
|
||||
.. code-block:: verilog
|
||||
:force:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue