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[EXAMPLES] Ported the mojo counter example to Zynq ZED board.

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Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
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James Walmsley 2013-10-27 21:48:39 +01:00
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techlibs/xilinx/example_zed_counter/README Normal file
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This is a simple example for Yosys synthesis targeting the ZED FPGA
development board [1, 2]. Simple script for xst-based synthesis (incl.
generation of reference edif files) and uploading to the board can be
found here [3].
[1] http://www.zedboard.org/
[2] https://www.xilinx.com/zynq/
[3] http://verilog.james.walms.co.uk/