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Add "verific -work" help message

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-08-22 17:22:24 +02:00
parent 4b02ee9162
commit 408077769f
1 changed files with 7 additions and 0 deletions
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7
frontends/verific/verific.cc
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@ -1706,11 +1706,18 @@ struct VerificPass : public Pass {
log("\n"); log("\n");
log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
log("\n"); log("\n");
log("\n");
log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
log("\n"); log("\n");
log("Load the specified VHDL files into Verific.\n"); log("Load the specified VHDL files into Verific.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
log("(default library when -work is not present: \"work\")\n");
log("\n");
log("\n");
log(" verific -vlog-incdir <directory>..\n"); log(" verific -vlog-incdir <directory>..\n");
log("\n"); log("\n");
log("Add Verilog include directories.\n"); log("Add Verilog include directories.\n");