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Fix issue with $mux in abc
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@ -1370,6 +1370,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
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RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
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cell->setPort(name, module->wire(remapped_name));
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}
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cell->fixup_parameters();
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design->select(module, cell);
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continue;
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}
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