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Display values of outputs
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parent
226dc659f0
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@ -885,6 +885,7 @@ struct SimWorker : SimShared
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SigMap sigmap(topmod);
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SigMap sigmap(topmod);
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log ("Get inputs\n");
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log ("Get inputs\n");
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std::map<Wire*,fstHandle> inputs;
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std::map<Wire*,fstHandle> inputs;
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std::map<Wire*,fstHandle> outputs;
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for (auto wire : topmod->wires()) {
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for (auto wire : topmod->wires()) {
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if (wire->port_input) {
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if (wire->port_input) {
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@ -892,6 +893,11 @@ struct SimWorker : SimShared
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log("Input %s\n",log_id(wire));
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log("Input %s\n",log_id(wire));
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inputs[wire] = id;
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inputs[wire] = id;
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}
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}
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if (wire->port_output) {
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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log("Output %s %d\n",log_id(wire), id);
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outputs[wire] = id;
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}
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}
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}
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fst->reconstruct(fst_clock);
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fst->reconstruct(fst_clock);
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@ -903,20 +909,12 @@ struct SimWorker : SimShared
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top->set_state(item.first, Const::from_string(v));
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top->set_state(item.first, Const::from_string(v));
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}
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}
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update();
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update();
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for(auto &item : outputs) {
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/*Wire *wire = topmod->wire("\\cnt");
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Const fst_val = Const::from_string(fst->valueAt(item.second, time));
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Const value = top->get_state(wire);
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Const sim_val = top->get_state(item.first);
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std::stringstream ss;
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log("%s %s\n", log_signal(fst_val), log_signal(sim_val));
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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}
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}
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log("%s\n",ss.str().c_str());*/
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}
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}
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}
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};
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};
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