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synth_lattice: Wire up cmp2softlogic as an option

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This commit is contained in:
Martin Povišer 2023-11-13 10:41:54 +01:00
parent f7d4a855c6
commit 3ffa4b5e5d
1 changed files with 12 additions and 0 deletions
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12
techlibs/lattice/synth_lattice.cc
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@ -127,6 +127,10 @@ struct SynthLatticePass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -cmp2softlogic\n");
log(" implement constant comparisons in soft logic, do not involve\n");
log(" hard carry chains\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@ -135,6 +139,7 @@ struct SynthLatticePass : public ScriptPass
string top_opt, edif_file, json_file, family;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
bool cmp2softlogic;
string postfix, arith_map, brams_map, dsp_map;
void clear_flags() override
@ -162,6 +167,7 @@ struct SynthLatticePass : public ScriptPass
brams_map = "";
dsp_map = "";
have_dsp = false;
cmp2softlogic = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -263,6 +269,10 @@ struct SynthLatticePass : public ScriptPass
no_rw_check = true;
continue;
}
if (args[argidx] == "-cmp2softlogic") {
cmp2softlogic = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -343,6 +353,8 @@ struct SynthLatticePass : public ScriptPass
run("peepopt");
run("opt_clean");
run("share");
if (cmp2softlogic)
run("techmap -map +/cmp2softlogic.v");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");