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Added "keep_hierarchy" attribute

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Clifford Wolf 2015-02-25 12:46:00 +01:00
parent 9ae21263f0
commit 3fe18c26cd
2 changed files with 54 additions and 14 deletions
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@ -288,6 +288,9 @@ Verilog Attributes and non-standard features
Setting the "keep" attribute on a module has the same effect as setting it
on all instances of the module.
- The "keep_hierarchy" attribute on cells and modules keeps the "flatten"
command from flattening the indicated cells and modules.
- The "init" attribute on wires is set by the frontend when a register is
initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
to add the necessary reset logic.