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	Signed extension
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					 2 changed files with 6 additions and 6 deletions
				
			
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					@ -50,7 +50,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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		if (st.ffA) {
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							if (st.ffA) {
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			SigSpec D = st.ffA->getPort("\\D");
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								SigSpec D = st.ffA->getPort("\\D");
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			cell->setPort("\\A", D.extend_u0(30));
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								cell->setPort("\\A", D.extend_u0(30, true));
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			cell->setParam("\\AREG", State::S1);
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								cell->setParam("\\AREG", State::S1);
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			if (st.ffA->type == "$dff")
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								if (st.ffA->type == "$dff")
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				cell->setPort("\\CEA2", State::S1);
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									cell->setPort("\\CEA2", State::S1);
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					@ -60,7 +60,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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		}
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							}
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		if (st.ffB) {
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							if (st.ffB) {
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			SigSpec D = st.ffB->getPort("\\D");
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								SigSpec D = st.ffB->getPort("\\D");
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			cell->setPort("\\B", D.extend_u0(18));
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								cell->setPort("\\B", D.extend_u0(18, true));
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			cell->setParam("\\BREG", State::S1);
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								cell->setParam("\\BREG", State::S1);
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			if (st.ffB->type == "$dff")
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								if (st.ffB->type == "$dff")
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				cell->setPort("\\CEB2", State::S1);
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									cell->setPort("\\CEB2", State::S1);
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					@ -9,10 +9,10 @@ endmatch
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match ffA
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					match ffA
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	select ffA->type.in($dff, $dffe)
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						select ffA->type.in($dff, $dffe)
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						select param(ffA, \CLK_POLARITY).as_bool()
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	// select nusers(port(ffA, \Q)) == 2
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						// select nusers(port(ffA, \Q)) == 2
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	index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A)
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						index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25)
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	// DSP48E1 does not support clock inversion
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						// DSP48E1 does not support clock inversion
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	index <Const> param(ffA, \CLK_POLARITY).as_bool() === true
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	optional
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						optional
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endmatch
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					endmatch
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					@ -23,9 +23,9 @@ endcode
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match ffB
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					match ffB
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	select ffB->type.in($dff, $dffe)
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						select ffB->type.in($dff, $dffe)
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						select param(ffB, \CLK_POLARITY).as_bool()
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	// select nusers(port(ffB, \Q)) == 2
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						// select nusers(port(ffB, \Q)) == 2
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	index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B)
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						index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B)
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	index <Const> param(ffB, \CLK_POLARITY).as_bool() === true
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	optional
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						optional
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endmatch
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					endmatch
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