mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Added stubnets example to manual prog chapter

Browse source
This commit is contained in:
Clifford Wolf 2013-08-07 02:19:35 +02:00
parent 653750faac
commit 3f5d7df603
3 changed files with 15 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

8
manual/CHAPTER_Prog.tex
View file

@ -11,3 +11,11 @@ with an example module.
\section{Internal Utility Libraries}
\section{Loadable Modules}
\section{Example Module}
\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}