More RTLIL::Cell API usage cleanups

backends/btor/btor.cc

@@ -387,8 +387,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* expr = &cell->get(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->connections().at(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* en = &cell->get(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -420,7 +420,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -444,7 +444,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -481,8 +481,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -515,8 +515,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -550,8 +550,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -559,7 +559,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -592,8 +592,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -628,9 +628,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\S")), 1);
+				int s = dump_sigspec(&cell->get(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -644,10 +644,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->connections().at(RTLIL::IdString("\\Q"));
+				const RTLIL::SigSpec* cell_output = &cell->get(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\D")), output_width);
+				int value = dump_sigspec(&cell->get(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -665,9 +665,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->get(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -685,7 +685,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -710,7 +710,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -722,13 +722,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->get(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->get(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -757,11 +757,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->get(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->connections().at(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->get(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -773,11 +773,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->get(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->connections().at(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->get(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -801,7 +801,7 @@ struct BtorDumper
 		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->get(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -809,11 +809,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\Q"));
+			output_sig = &cell->get(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\Y"));
+			output_sig = &cell->get(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}

backends/spice/spice.cc

@@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 				log_assert(wire != NULL);
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
 				if (cell->has(wire->name)) {
-					sig = sigmap(cell->connections().at(wire->name));
+					sig = sigmap(cell->get(wire->name));
 					sig.extend(wire->width, false);
 				}
 				port_sigs.push_back(sig);

passes/opt/opt_const.cc

@@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 	bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
 
 	RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
-	RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
+	RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
 	RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
 
 	if (extend_u0) {

passes/sat/expose.cc

@@ -629,7 +629,7 @@ struct ExposePass : public Pass {
 
 							RTLIL::SigSpec sig;
 							if (cell->has(p->name))
-								sig = cell->connections().at(p->name);
+								sig = cell->get(p->name);
 							sig.extend(w->width);
 							if (w->port_input)
 								module->connect(RTLIL::SigSig(sig, w));

passes/techmap/extract.cc

@@ -128,7 +128,7 @@ namespace
 				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -324,7 +324,7 @@ namespace
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
+						RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1);
 						RTLIL::SigSpec new_sig = cell->get(port.first);
 						new_sig.replace(port.second, bitsig);
 						cell->set(port.first, new_sig);