3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00

More RTLIL::Cell API usage cleanups

This commit is contained in:
Clifford Wolf 2014-07-26 16:14:02 +02:00
parent 97a59851a6
commit 3f4e3ca8ad
5 changed files with 39 additions and 39 deletions

View file

@ -629,7 +629,7 @@ struct ExposePass : public Pass {
RTLIL::SigSpec sig;
if (cell->has(p->name))
sig = cell->connections().at(p->name);
sig = cell->get(p->name);
sig.extend(w->width);
if (w->port_input)
module->connect(RTLIL::SigSig(sig, w));