mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-27 19:05:52 +00:00
More RTLIL::Cell API usage cleanups
This commit is contained in:
parent
97a59851a6
commit
3f4e3ca8ad
5 changed files with 39 additions and 39 deletions
|
@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
|
|||
bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
|
||||
|
||||
RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
|
||||
RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
|
||||
RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
|
||||
RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
|
||||
|
||||
if (extend_u0) {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue