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More RTLIL::Cell API usage cleanups

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This commit is contained in:
Clifford Wolf 2014-07-26 16:14:02 +02:00
parent 97a59851a6
commit 3f4e3ca8ad
5 changed files with 39 additions and 39 deletions
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2
passes/opt/opt_const.cc
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@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
if (extend_u0) {

2
passes/sat/expose.cc
View file

@ -629,7 +629,7 @@ struct ExposePass : public Pass {
RTLIL::SigSpec sig;
if (cell->has(p->name))
sig = cell->connections().at(p->name);
sig = cell->get(p->name);
sig.extend(w->width);
if (w->port_input)
module->connect(RTLIL::SigSig(sig, w));

4
passes/techmap/extract.cc
View file

@ -128,7 +128,7 @@ namespace
for (auto &conn : needleCell->connections())
{
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first));
RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@ -324,7 +324,7 @@ namespace
if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
for (int i = 0; i < sig.size(); i++)
for (auto &port : sig2port.find(sig[i])) {
RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1);
RTLIL::SigSpec new_sig = cell->get(port.first);
new_sig.replace(port.second, bitsig);
cell->set(port.first, new_sig);