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More RTLIL::Cell API usage cleanups

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This commit is contained in:
Clifford Wolf 2014-07-26 16:14:02 +02:00
parent 97a59851a6
commit 3f4e3ca8ad
5 changed files with 39 additions and 39 deletions
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2
backends/spice/spice.cc
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@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
if (cell->has(wire->name)) {
sig = sigmap(cell->connections().at(wire->name));
sig = sigmap(cell->get(wire->name));
sig.extend(wire->width, false);
}
port_sigs.push_back(sig);