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ice40: match memory inference attribute values case insensitive.

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LSE/Synplify use case insensitive matching.
This commit is contained in:
whitequark 2020-01-01 07:20:06 +00:00
parent 60f047f136
commit 3f4460a186
2 changed files with 7 additions and 0 deletions
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1
techlibs/ice40/brams.txt
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@ -30,6 +30,7 @@ endbram
# The syn_* attributes are described in: # The syn_* attributes are described in:
# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx # https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
attr_icase 1
match $__ICE40_RAM4K_M0 match $__ICE40_RAM4K_M0
# implicitly requested RAM or ROM # implicitly requested RAM or ROM

6
tests/arch/ice40/memories.ys
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@ -34,6 +34,12 @@ setattr -set syn_ramstyle "block_ram" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K # any case works
design -reset; read_verilog ../common/blockram.v design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
setattr -set ram_block 1 m:memory setattr -set ram_block 1 m:memory