mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 03:33:36 +00:00
synth_nexus to synth_lattice
This commit is contained in:
Miodrag Milanovic
parent
72bec94ef4
commit
3f2e3a8f57
7
Makefile
7
Makefile
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@ -575,6 +575,13 @@ $(subst //,/,$(1)/$(notdir $(2))): $(2)
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$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(notdir $(2)))
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endef
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define add_share_file_and_rename
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EXTRA_TARGETS += $(subst //,/,$(1)/$(3))
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$(subst //,/,$(1)/$(3)): $(2)
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$$(P) mkdir -p $(1)
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$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(3))
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endef
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define add_gen_share_file
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EXTRA_TARGETS += $(subst //,/,$(1)/$(notdir $(2)))
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$(subst //,/,$(1)/$(notdir $(2))): $(2)
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@ -4,25 +4,41 @@ OBJS += techlibs/lattice/lattice_gsr.o
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_trellis.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/parse_init.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3d.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_trellis.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_trellis.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_nexus.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_map_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_nexus.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_nexus.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_nexus.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_nexus.v))
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$(eval $(call add_share_file,share/nexus,techlibs/lattice/parse_init.vh))
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$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_sim_nexus.v,cells_sim.v))
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$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_bb_nexus.v,cells_xtra.v))
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@ -280,7 +280,7 @@ if __name__ == '__main__':
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for device, cells in devices:
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xtract_cells_decl(device, cells, dirs, out)
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with open('cells_xtra.v', 'w') as f:
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f.write('// Created by cells_xtra.py from Lattice models\n')
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with open('cells_bb_nexus.v', 'w') as f:
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f.write('// Created by cells_xtra_nexus.py from Lattice models\n')
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f.write('\n')
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f.write(out.getvalue())
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@ -35,13 +35,32 @@ struct SynthLatticePass : public ScriptPass
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RTLIL::constpad["synth_lattice.abc9.W"] = "300";
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}
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struct DSPRule {
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int a_maxwidth;
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int b_maxwidth;
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int a_minwidth;
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int b_minwidth;
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std::string prim;
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};
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const std::vector<DSPRule> dsp_rules_nexus = {
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{36, 36, 22, 22, "$__NX_MUL36X36"},
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{36, 18, 22, 10, "$__NX_MUL36X18"},
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{18, 18, 10, 4, "$__NX_MUL18X18"},
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{18, 18, 4, 10, "$__NX_MUL18X18"},
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{ 9, 9, 4, 4, "$__NX_MUL9X9"},
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};
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const std::vector<DSPRule> dsp_rules_ecp5 = {
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{18, 18, 2, 2, "$__MUL18X18"},
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};
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_lattice [options]\n");
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log("\n");
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log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n");
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log("This command runs synthesis for Lattice FPGAs (excluding iCE40).\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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@ -54,6 +73,8 @@ struct SynthLatticePass : public ScriptPass
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log(" - xo2: MachXO2\n");
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log(" - xo3: MachXO3L/LF\n");
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log(" - xo3d: MachXO3D\n");
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log(" - lifcl: CrossLink-NX\n");
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log(" - lfd2nx: Certus-NX\n");
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//log(" - xo: MachXO (EXPERIMENTAL)\n");
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//log(" - pm: Platform Manager (EXPERIMENTAL)\n");
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//log(" - pm2: Platform Manager 2 (EXPERIMENTAL)\n");
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@ -118,9 +139,13 @@ struct SynthLatticePass : public ScriptPass
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log("\n");
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log(" -iopad\n");
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log(" insert IO buffers\n");
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log(" (by default enabled on Nexus FPGAs)\n");
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log("\n");
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log(" -noiopad\n");
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log(" do not insert IO buffers\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not map multipliers to MULT18X18D\n");
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log(" do not infer DSP multipliers\n");
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log("\n");
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log(" -no-rw-check\n");
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log(" marks all recognized read ports as \"return don't-care value on\n");
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@ -135,7 +160,9 @@ struct SynthLatticePass : public ScriptPass
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string top_opt, edif_file, json_file, family;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
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string postfix, arith_map, brams_map, dsp_map;
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string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc;
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bool is_nexus;
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std::vector<DSPRule> dsp_rules;
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void clear_flags() override
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{
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@ -162,12 +189,17 @@ struct SynthLatticePass : public ScriptPass
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brams_map = "";
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dsp_map = "";
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have_dsp = false;
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is_nexus = false;
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map_ram_default = "";
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cells_map = "";
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widelut_abc = "4:7";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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bool force_widelut = false;
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bool force_iopad = false;
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clear_flags();
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size_t argidx;
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@ -253,6 +285,12 @@ struct SynthLatticePass : public ScriptPass
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}
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if (args[argidx] == "-iopad") {
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iopad = true;
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force_iopad = true;
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continue;
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}
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if (args[argidx] == "-noiopad") {
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iopad = false;
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force_iopad = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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@ -275,7 +313,9 @@ struct SynthLatticePass : public ScriptPass
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arith_map = "_ccu2c";
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brams_map = "_16kd";
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dsp_map = "_18x18";
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dsp_rules = dsp_rules_ecp5;
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have_dsp = true;
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cells_map = "_trellis";
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} else if (family == "xo2" ||
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family == "xo3" ||
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family == "xo3d" /* ||
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@ -283,8 +323,22 @@ struct SynthLatticePass : public ScriptPass
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postfix = "_" + family;
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arith_map = "_ccu2d";
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brams_map = "_8kc";
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cells_map = "_trellis";
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have_dsp = false;
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if (!force_widelut) nowidelut = true;
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} else if (family == "lifcl" ||
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family == "lfd2nx") {
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is_nexus = true;
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postfix = "_nexus";
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arith_map = "_nexus";
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brams_map = "_nexus";
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dsp_map = "_nexus";
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dsp_rules = dsp_rules_nexus;
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have_dsp = true;
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map_ram_default = " -no-auto-huge";
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cells_map = "_nexus";
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widelut_abc = "4:5";
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if (!force_iopad) iopad = true;
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/* } else if (family == "xo" ||
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family == "pm") {
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} else if (family == "xp" ||
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@ -346,10 +400,19 @@ struct SynthLatticePass : public ScriptPass
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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if (have_dsp && !nodsp) {
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run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
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run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
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if (help_mode) {
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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run("techmap -map +/lattice/dsp_map" + dsp_map + ".v", "(unless -nodsp)");
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} else if (have_dsp && !nodsp) {
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for (const auto &rule : dsp_rules) {
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run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
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rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim.c_str()));
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run("chtype -set $mul t:$__soft_mul");
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}
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run("techmap -map +/lattice/dsp_map" + dsp_map + ".v");
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}
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run("alumacc");
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run("opt");
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run("memory -nomap" + no_rw_check_opt);
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@ -358,15 +421,20 @@ struct SynthLatticePass : public ScriptPass
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if (check_label("map_ram"))
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{
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std::string args = "";
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std::string args = map_ram_default;
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if (nobram)
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args += " -no-auto-block";
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if (nolutram)
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args += " -no-auto-distributed";
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if (help_mode)
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args += " [-no-auto-block] [-no-auto-distributed]";
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run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
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run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v");
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if (!is_nexus) {
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run("memory_libmap -lib +/lattice/lutrams" + cells_map + ".txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
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run("techmap -map +/lattice/lutrams_map" + cells_map + ".v -map +/lattice/brams_map" + brams_map + ".v");
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} else {
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run("memory_libmap -lib +/lattice/lutrams" + cells_map + ".txt -lib +/lattice/brams" + brams_map + ".txt -lib +/lattice/lrams_nexus.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
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run("techmap -map +/lattice/lutrams_map" + cells_map + ".v -map +/lattice/brams_map" + brams_map + ".v -map +/lattice/lrams_map_nexus.v");
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}
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}
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if (check_label("map_ffram"))
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@ -395,26 +463,36 @@ struct SynthLatticePass : public ScriptPass
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if (check_label("map_ffs"))
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{
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run("opt_clean");
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std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
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if (help_mode) {
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dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
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} else if (!nodffe) {
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dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
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}
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if (help_mode) {
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dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
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} else if (asyncprld) {
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dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
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if (!is_nexus) {
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std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
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if (help_mode) {
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dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
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} else if (!nodffe) {
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dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
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}
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if (help_mode) {
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dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
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} else if (asyncprld) {
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dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
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} else {
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dfflegalize_args += " -cell $_DLATCH_?_ x";
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}
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run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
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} else {
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dfflegalize_args += " -cell $_DLATCH_?_ x";
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std::string dfflegalize_args = " -cell $_DFF_P_ 01 -cell $_DFF_PP?_ r -cell $_SDFF_PP?_ r -cell $_DLATCH_?_ x";
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if (help_mode) {
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dfflegalize_args += " [-cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r]";
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} else if (!nodffe) {
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dfflegalize_args += " -cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r";
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}
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run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)");
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}
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run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
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if ((abc9 && dff) || help_mode)
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run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
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run("techmap -D NO_LUT -map +/lattice/cells_map.v");
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run("techmap -D NO_LUT -map +/lattice/cells_map" + cells_map + ".v");
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run("opt_expr -undriven -mux_undef");
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run("simplemap");
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run("lattice_gsr");
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if (!is_nexus) run("lattice_gsr");
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run("attrmvcp -copy -attr syn_useioff");
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run("opt_clean");
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}
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@ -445,7 +523,7 @@ struct SynthLatticePass : public ScriptPass
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if (nowidelut)
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abc_args += " -lut 4";
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else
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abc_args += " -lut 4:7";
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abc_args += " -lut " + widelut_abc;
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if (dff)
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abc_args += " -dff";
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run("abc" + abc_args);
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@ -455,8 +533,14 @@ struct SynthLatticePass : public ScriptPass
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if (check_label("map_cells"))
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{
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run("techmap -map +/lattice/cells_map.v");
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run("opt_lut_ins -tech lattice");
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run("techmap -map +/lattice/cells_map" + cells_map + ".v");
|
||||
if (is_nexus) {
|
||||
// This is needed for Radiant, but perhaps not optimal for nextpnr...
|
||||
run("setundef -zero");
|
||||
run("hilomap -singleton -hicell VHI Z -locell VLO Z");
|
||||
} else {
|
||||
run("opt_lut_ins -tech lattice");
|
||||
}
|
||||
run("clean");
|
||||
}
|
||||
|
||||
|
|
@ -483,6 +567,33 @@ struct SynthLatticePass : public ScriptPass
|
|||
}
|
||||
} SynthLatticePass;
|
||||
|
||||
struct SynthNexusPass : public Pass
|
||||
{
|
||||
SynthNexusPass() : Pass("synth_nexus", "synthesis for Nexus FPGAs") { }
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_nexus [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for Nexus FPGAs.\n");
|
||||
log("\n");
|
||||
log("This is wrapper pass, for details take a look at help message for synth_lattice.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
args[0] = "synth_lattice";
|
||||
args.insert(args.begin()+1, std::string());
|
||||
args.insert(args.begin()+1, std::string());
|
||||
args[1] = "-family";
|
||||
args[2] = "lifcl";
|
||||
Pass::call(design, args);
|
||||
}
|
||||
} SynthNexusPass;
|
||||
|
||||
/*
|
||||
struct SynthEcp5Pass : public Pass
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
OBJS += techlibs/nexus/synth_nexus.o
|
||||
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/cells_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/parse_init.vh))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/lutrams_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/lutrams.txt))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/brams_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/brams.txt))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/lrams_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/lrams.txt))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/arith_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/latches_map.v))
|
||||
$(eval $(call add_share_file,share/nexus,techlibs/nexus/dsp_map.v))
|
||||
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
module \$_DLATCH_N_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = !E ? D : Q;
|
||||
endmodule
|
||||
|
||||
module \$_DLATCH_P_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = E ? D : Q;
|
||||
endmodule
|
||||
|
|
@ -1,417 +0,0 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2020 gatecat <gatecat@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthNexusPass : public ScriptPass
|
||||
{
|
||||
SynthNexusPass() : ScriptPass("synth_nexus", "synthesis for Lattice Nexus FPGAs") { }
|
||||
|
||||
void on_register() override
|
||||
{
|
||||
RTLIL::constpad["synth_nexus.abc9.W"] = "300";
|
||||
}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_nexus [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for Lattice Nexus FPGAs.\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -family <device>\n");
|
||||
log(" run synthesis for the specified Nexus device\n");
|
||||
log(" supported values: lifcl, lfd2nx\n");
|
||||
log("\n");
|
||||
log(" -json <file>\n");
|
||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -vm <file>\n");
|
||||
log(" write the design to the specified structural Verilog file. writing of\n");
|
||||
log(" an output file is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -dff\n");
|
||||
log(" run 'abc'/'abc9' with -dff option\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log(" -noccu2\n");
|
||||
log(" do not use CCU2 cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nodffe\n");
|
||||
log(" do not use flipflops with CE in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nolram\n");
|
||||
log(" do not use large RAM cells in output netlist\n");
|
||||
log(" note that large RAM must be explicitly requested with a (* lram *)\n");
|
||||
log(" attribute on the memory.\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nolutram\n");
|
||||
log(" do not use LUT RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nowidelut\n");
|
||||
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
|
||||
log("\n");
|
||||
log(" -noiopad\n");
|
||||
log(" do not insert IO buffers\n");
|
||||
log("\n");
|
||||
log(" -nodsp\n");
|
||||
log(" do not infer DSP multipliers\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, json_file, vm_file, family;
|
||||
bool noccu2, nodffe, nolram, nobram, nolutram, nowidelut, noiopad, nodsp, flatten, dff, retime, abc9;
|
||||
|
||||
void clear_flags() override
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
family = "lifcl";
|
||||
json_file = "";
|
||||
vm_file = "";
|
||||
noccu2 = false;
|
||||
nodffe = false;
|
||||
nolram = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
nowidelut = false;
|
||||
noiopad = false;
|
||||
nodsp = false;
|
||||
flatten = true;
|
||||
dff = false;
|
||||
retime = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
string run_from, run_to;
|
||||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
||||
json_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-vm" && argidx+1 < args.size()) {
|
||||
vm_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
continue;
|
||||
}
|
||||
if ((args[argidx] == "-family") && argidx+1 < args.size()) {
|
||||
family = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten") {
|
||||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dff") {
|
||||
dff = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodsp") {
|
||||
nodsp = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-retime") {
|
||||
retime = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noccu2") {
|
||||
noccu2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodffe") {
|
||||
nodffe = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nolram") {
|
||||
nolram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nolutram") {
|
||||
nolutram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nowidelut") {
|
||||
nowidelut = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noiopad") {
|
||||
noiopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
if (abc9 && retime)
|
||||
log_cmd_error("-retime option not currently compatible with -abc9!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_NEXUS pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
struct DSPRule {
|
||||
int a_maxwidth;
|
||||
int b_maxwidth;
|
||||
int a_minwidth;
|
||||
int b_minwidth;
|
||||
std::string prim;
|
||||
};
|
||||
|
||||
const std::vector<DSPRule> dsp_rules = {
|
||||
{36, 36, 22, 22, "$__NX_MUL36X36"},
|
||||
{36, 18, 22, 10, "$__NX_MUL36X18"},
|
||||
{18, 18, 10, 4, "$__NX_MUL18X18"},
|
||||
{18, 18, 4, 10, "$__NX_MUL18X18"},
|
||||
{ 9, 9, 4, 4, "$__NX_MUL9X9"},
|
||||
};
|
||||
|
||||
void script() override
|
||||
{
|
||||
|
||||
if (family != "lifcl" && family != "lfd2nx")
|
||||
log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family.c_str());
|
||||
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib -specify +/nexus/cells_sim.v +/nexus/cells_xtra.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("proc");
|
||||
if (flatten || help_mode)
|
||||
run("flatten");
|
||||
run("tribuf -logic");
|
||||
run("deminout");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
run("check");
|
||||
run("opt -nodffe -nosdff");
|
||||
run("fsm");
|
||||
run("opt");
|
||||
run("wreduce");
|
||||
run("peepopt");
|
||||
run("opt_clean");
|
||||
run("share");
|
||||
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
|
||||
if (help_mode) {
|
||||
run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
|
||||
run("techmap -map +/nexus/dsp_map.v", "(unless -nodsp)");
|
||||
} else if (!nodsp) {
|
||||
for (const auto &rule : dsp_rules) {
|
||||
run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
|
||||
rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim.c_str()));
|
||||
run("chtype -set $mul t:$__soft_mul");
|
||||
}
|
||||
run("techmap -map +/nexus/dsp_map.v");
|
||||
}
|
||||
|
||||
run("alumacc");
|
||||
run("opt");
|
||||
run("memory -nomap");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_ram"))
|
||||
{
|
||||
std::string args = "";
|
||||
args += " -no-auto-huge";
|
||||
if (nobram)
|
||||
args += " -no-auto-block";
|
||||
if (nolutram)
|
||||
args += " -no-auto-distributed";
|
||||
if (help_mode)
|
||||
args += " [-no-auto-block] [-no-auto-distributed]";
|
||||
run("memory_libmap -lib +/nexus/lutrams.txt -lib +/nexus/brams.txt -lib +/nexus/lrams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
||||
run("techmap -map +/nexus/lutrams_map.v -map +/nexus/brams_map.v -map +/nexus/lrams_map.v");
|
||||
}
|
||||
|
||||
if (check_label("map_ffram"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
}
|
||||
|
||||
if (check_label("map_gates"))
|
||||
{
|
||||
if (noccu2)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/nexus/arith_map.v");
|
||||
if (help_mode || !noiopad)
|
||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(skip if '-noiopad')");
|
||||
run("opt -fast");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("opt_clean");
|
||||
std::string dfflegalize_args = " -cell $_DFF_P_ 01 -cell $_DFF_PP?_ r -cell $_SDFF_PP?_ r -cell $_DLATCH_?_ x";
|
||||
if (help_mode) {
|
||||
dfflegalize_args += " [-cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r]";
|
||||
} else if (!nodffe) {
|
||||
dfflegalize_args += " -cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r";
|
||||
}
|
||||
run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)");
|
||||
if ((abc9 && dff) || help_mode)
|
||||
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff");
|
||||
run("techmap -D NO_LUT -map +/nexus/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
run("techmap -map +/nexus/latches_map.v");
|
||||
|
||||
if (abc9) {
|
||||
std::string abc9_opts;
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
std::string k = "synth_nexus.abc9.W";
|
||||
if (active_design && active_design->scratchpad.count(k))
|
||||
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
||||
else
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
if (dff)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
} else {
|
||||
std::string abc_args = " -dress";
|
||||
if (nowidelut)
|
||||
abc_args += " -lut 4";
|
||||
else
|
||||
abc_args += " -lut 4:5";
|
||||
if (dff)
|
||||
abc_args += " -dff";
|
||||
run("abc" + abc_args);
|
||||
}
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("map_cells"))
|
||||
{
|
||||
run("techmap -map +/nexus/cells_map.v");
|
||||
|
||||
// This is needed for Radiant, but perhaps not optimal for nextpnr...
|
||||
run("setundef -zero");
|
||||
|
||||
run("hilomap -singleton -hicell VHI Z -locell VLO Z");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
{
|
||||
run("autoname");
|
||||
run("hierarchy -check");
|
||||
run("stat");
|
||||
run("check -noinit");
|
||||
run("blackbox =A:whitebox");
|
||||
}
|
||||
|
||||
if (check_label("json"))
|
||||
{
|
||||
if (!json_file.empty() || help_mode)
|
||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("vm"))
|
||||
{
|
||||
if (!vm_file.empty() || help_mode)
|
||||
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vm_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthNexusPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Reference in a new issue