From 3f1ee3e0ae0436e8e493e06d64a70075f49794da Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 10 Feb 2025 12:01:26 +0100
Subject: [PATCH] abstract: -state refactor sigbit rep pool collection

---
 passes/cmds/abstract.cc | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc
index 706636d59..743ff2dd8 100644
--- a/passes/cmds/abstract.cc
+++ b/passes/cmds/abstract.cc
@@ -43,10 +43,7 @@ bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, E
 	return true;
 }
 
-unsigned int abstract_state(Module* mod, EnableLogic enable) {
-	CellTypes ct;
-	ct.setup_internals_ff();
-	SigMap sigmap(mod);
+pool<SigBit> gather_selected_reps(Module* mod, SigMap& sigmap) {
 	pool<SigBit> selected_representatives;
 
 	// Collect reps for all wire bits of selected wires
@@ -60,6 +57,14 @@ unsigned int abstract_state(Module* mod, EnableLogic enable) {
 			if (cell->output(conn.first))
 				for (auto bit : conn.second.bits())
 					selected_representatives.insert(sigmap(bit));
+	return selected_representatives;
+}
+
+unsigned int abstract_state(Module* mod, EnableLogic enable) {
+	CellTypes ct;
+	ct.setup_internals_ff();
+	SigMap sigmap(mod);
+	pool<SigBit> selected_representatives = gather_selected_reps(mod, sigmap);
 
 	unsigned int changed = 0;
 	std::vector<FfData> ffs;