mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 11:45:41 +00:00
Code Activity

Improve the naming for opt_reduce

Browse source
This commit is contained in:
Akash Levy 2025-03-31 01:22:42 -07:00
parent f72d27fae0
commit 3f00e57076
1 changed files with 3 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/opt/opt_reduce.cc
View file

@ -128,13 +128,14 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID2_SUFFIX("reduce_or"), ID($reduce_or)); // SILIMATE: Improve the naming
reduce_or_cell->setPort(ID::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
reduce_or_cell->set_src_attribute(cell->get_src_attribute()); // SILIMATE: Improve the naming
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID2_SUFFIX("reduce_or_wire")); // SILIMATE: Improve the naming
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->setPort(ID::Y, this_s);
}