From 3eef6450f10b672c95864b1e35409febfd501ccd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 5 Feb 2024 14:46:12 +0100
Subject: [PATCH] check: Add coarse-grain false positive test

---
 tests/various/check.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/various/check.ys

diff --git a/tests/various/check.ys b/tests/various/check.ys
new file mode 100644
index 000000000..cdc944ed3
--- /dev/null
+++ b/tests/various/check.ys
@@ -0,0 +1,12 @@
+design -reset
+read_verilog <<EOF
+module top(input clk, input a, input b, output [9:0] x);
+	wire [9:0] ripple;
+	reg [9:0] prev_ripple = 9'b0;
+
+	always @(posedge clk) prev_ripple <= ripple;
+	assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
+	assign x = ripple[9] + b;
+endmodule
+EOF
+check -assert