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Merge pull request #1379 from mmicko/sim_models

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Added simulation models for Efinix and Anlogic
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Eddie Hung 2019-09-18 10:04:27 -07:00 • committed by GitHub
commit 3ec28ec53a
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2 changed files with 162 additions and 7 deletions
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99
techlibs/anlogic/cells_sim.v
View file

@ -1,5 +1,5 @@
module AL_MAP_SEQ (
output q,
output reg q,
input ce,
input clk,
input sr,
@ -9,6 +9,71 @@ module AL_MAP_SEQ (
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
wire clk_ce;
assign clk_ce = ce ? clk : 1'b0;
wire srmux;
generate
case (SRMUX)
"SR": assign srmux = sr;
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
endgenerate
wire regset;
generate
case (REGSET)
"RESET": assign regset = 1'b0;
"SET": assign regset = 1'b1;
default: assign regset = 1'b0;
endcase
endgenerate
initial q = regset;
generate
if (DFFMODE == "FF")
begin
if (SRMODE == "ASYNC")
begin
always @(posedge clk_ce, posedge srmux)
if (srmux)
q <= regset;
else
q <= d;
end
else
begin
always @(posedge clk_ce)
if (srmux)
q <= regset;
else
q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
if (SRMODE == "ASYNC")
begin
always @(clk_ce, srmux)
if (srmux)
q <= regset;
else
q <= d;
end
else
begin
always @(clk_ce)
if (srmux)
q <= regset;
else
q <= d;
end
end
endgenerate
endmodule
module AL_MAP_LUT1 (
@ -17,7 +82,8 @@ module AL_MAP_LUT1 (
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = INIT >> a;
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
@ -27,7 +93,9 @@ module AL_MAP_LUT2 (
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
assign o = INIT >> {b, a};
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
@ -38,7 +106,10 @@ module AL_MAP_LUT3 (
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
assign o = INIT >> {c, b, a};
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
@ -50,7 +121,11 @@ module AL_MAP_LUT4 (
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
assign o = INIT >> {d, c, b, a};
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
@ -100,4 +175,18 @@ module AL_MAP_ADDER (
output [1:0] o
);
parameter ALUTYPE = "ADD";
generate
case (ALUTYPE)
"ADD": assign o = a + b + c;
"SUB": assign o = a - b - c;
"A_LE_B": assign o = a - b - c;
"ADD_CARRY": assign o = { a, 1'b0 };
"SUB_CARRY": assign o = { ~a, 1'b0 };
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endmodule

70
techlibs/efinix/cells_sim.v
View file

@ -5,7 +5,12 @@ module EFX_LUT4(
input I2,
input I3
);
parameter LUTMASK = 16'h0000;
parameter LUTMASK = 16'h0000;
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
@ -17,10 +22,18 @@ module EFX_ADD(
);
parameter I0_POLARITY = 1;
parameter I1_POLARITY = 1;
wire i0;
wire i1;
assign i0 = I0_POLARITY ? I0 : ~I0;
assign i1 = I1_POLARITY ? I1 : ~I1;
assign {CO, O} = i0 + i1 + CI;
endmodule
module EFX_FF(
output Q,
output reg Q,
input D,
input CE,
input CLK,
@ -33,6 +46,53 @@ module EFX_FF(
parameter SR_VALUE = 0;
parameter SR_SYNC_PRIORITY = 0;
parameter D_POLARITY = 1;
wire clk;
wire ce;
wire sr;
wire d;
wire prio;
wire sync;
wire async;
assign clk = CLK_POLARITY ? CLK : ~CLK;
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
generate
if (SR_SYNC == 1)
begin
if (SR_SYNC_PRIORITY == 1)
begin
always @(posedge clk)
if (sr)
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
else
begin
always @(posedge clk)
if (ce)
begin
if (sr)
Q <= SR_VALUE;
else
Q <= d;
end
end
end
else
begin
always @(posedge clk or posedge sr)
if (sr)
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
endgenerate
endmodule
module EFX_GBUFCE(
@ -41,6 +101,12 @@ module EFX_GBUFCE(
output O
);
parameter CE_POLARITY = 1'b1;
wire ce;
assign ce = CE_POLARITY ? CE : ~CE;
assign O = I & ce;
endmodule
module EFX_RAM_5K(