From dd8b412833b85cfffb6371b1f75340233b83a0bd Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 30 Aug 2022 13:58:09 +0200
Subject: [PATCH 1/2] simplify: Do not recursively simplify AST_CELL within
 AST_CELLARRAY

Otherwise the AST_CELL simplification uses the wrong celltype before the
AST_CELLARRAY simplification has a chance to unroll it and change it to
the $array celltype.
---
 frontends/ast/simplify.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 57237f4b3..91c4d1472 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1627,6 +1627,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			break;
 		if (type == AST_GENBLOCK)
 			break;
+		if (type == AST_CELLARRAY && children[i]->type == AST_CELL)
+			continue;
 		if (type == AST_BLOCK && !str.empty())
 			break;
 		if (type == AST_PREFIX && i >= 1)

From cf3570abde2351ae15892eb7318eccec48582a5d Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Wed, 7 Dec 2022 18:41:55 +0100
Subject: [PATCH 2/2] simplify: regression test for AST_CELLARRAY
 simplification issue

---
 tests/various/cellarray_array_connections.ys | 45 ++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 tests/various/cellarray_array_connections.ys

diff --git a/tests/various/cellarray_array_connections.ys b/tests/various/cellarray_array_connections.ys
new file mode 100644
index 000000000..ef36a9a45
--- /dev/null
+++ b/tests/various/cellarray_array_connections.ys
@@ -0,0 +1,45 @@
+# Regression test for #3467
+read_verilog <<EOT
+
+module bit_buf (
+    input wire bit_in,
+    output wire bit_out
+);
+    assign bit_out = bit_in;
+endmodule
+
+module top (
+	input wire [3:0] data_in,
+	output wire [3:0] data_out
+);
+
+    wire [3:0] data [0:4];
+
+    assign data[0] = data_in;
+    assign data_out = data[4];
+
+	genvar i;
+	generate
+		for (i=0; i<=3; i=i+1) begin
+			bit_buf bit_buf_instance[3:0] (
+				.bit_in(data[i]),
+				.bit_out(data[i + 1])
+			);
+		end
+	endgenerate
+endmodule
+
+module top2 (
+	input wire [3:0] data_in,
+	output wire [3:0] data_out
+);
+    assign data_out = data_in;
+endmodule
+
+EOT
+
+hierarchy
+proc
+
+miter -equiv -make_assert -flatten top top2 miter
+sat -prove-asserts -verify miter