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make note that it is for latch mode

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Miodrag Milanovic 2019-09-18 17:48:16 +02:00
parent b0ca6de472
commit 3e9449cb0b
1 changed files with 1 additions and 0 deletions
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techlibs/anlogic/cells_sim.v
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@ -55,6 +55,7 @@ module AL_MAP_SEQ (
end end
else else
begin begin
// DFFMODE == "LATCH"
if (SRMODE == "ASYNC") if (SRMODE == "ASYNC")
begin begin
always @(clk_ce, srmux) always @(clk_ce, srmux)