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Add "check -allow-tbuf"

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-10-03 11:49:56 +02:00
parent 45e4c040d7
commit 3e27b2846b
1 changed files with 22 additions and 8 deletions
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30
passes/cmds/check.cc
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@ -41,17 +41,24 @@ struct CheckPass : public Pass {
log("\n"); log("\n");
log(" - used wires that do not have a driver\n"); log(" - used wires that do not have a driver\n");
log("\n"); log("\n");
log("When called with -noinit then this command also checks for wires which have\n"); log("Options:\n");
log("the 'init' attribute set.\n");
log("\n"); log("\n");
log("When called with -initdrv then this command also checks for wires which have\n"); log(" -noinit\n");
log("the 'init' attribute set and aren't driven by a FF cell type.\n"); log(" Also check for wires which have the 'init' attribute set.\n");
log("\n"); log("\n");
log("When called with -mapped then this command also checks for internal cells\n"); log(" -initdrv\n");
log("that have not been mapped to cells of the target architecture.\n"); log(" Also check for wires that have the 'init' attribute set and are not\n");
log(" driven by an FF cell type.\n");
log("\n"); log("\n");
log("When called with -assert then the command will produce an error if any\n"); log(" -mapped\n");
log("problems are found in the current design.\n"); log(" Also check for internal cells that have not been mapped to cells of the\n");
log(" target architecture.\n");
log("\n");
log(" -allow-tbuf\n");
log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n");
log("\n");
log(" -assert\n");
log(" Produce a runtime error if any problems are found in the current design.\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -60,6 +67,7 @@ struct CheckPass : public Pass {
bool noinit = false; bool noinit = false;
bool initdrv = false; bool initdrv = false;
bool mapped = false; bool mapped = false;
bool allow_tbuf = false;
bool assert_mode = false; bool assert_mode = false;
size_t argidx; size_t argidx;
@ -76,6 +84,10 @@ struct CheckPass : public Pass {
mapped = true; mapped = true;
continue; continue;
} }
if (args[argidx] == "-allow-tbuf") {
allow_tbuf = true;
continue;
}
if (args[argidx] == "-assert") { if (args[argidx] == "-assert") {
assert_mode = true; assert_mode = true;
continue; continue;
@ -145,8 +157,10 @@ struct CheckPass : public Pass {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type)); log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
counter++; counter++;
cell_allowed:;
} }
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
SigSpec sig = sigmap(conn.second); SigSpec sig = sigmap(conn.second);