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Fixed tests

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This commit is contained in:
Miodrag Milanovic 2019-11-11 15:41:33 +01:00
parent 362f4f996d
commit 3e0ffe05a7
5 changed files with 34 additions and 17 deletions
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6
tests/arch/xilinx/fsm.ys
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@ -2,7 +2,11 @@ read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module