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Fixed tests

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This commit is contained in:
Miodrag Milanovic 2019-11-11 15:41:33 +01:00
parent 362f4f996d
commit 3e0ffe05a7
5 changed files with 34 additions and 17 deletions
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11
tests/arch/anlogic/fsm.ys
View file

@ -1,12 +1,15 @@
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
#flatten
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
flatten
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT2
select -assert-count 5 t:AL_MAP_LUT5
select -assert-count 1 t:AL_MAP_LUT6

13
tests/arch/ecp5/fsm.ys
View file

@ -2,11 +2,16 @@ read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 13 t:LUT4
select -assert-count 5 t:PFUMX
select -assert-count 5 t:TRELLIS_FF
select -assert-count 15 t:LUT4
select -assert-count 6 t:PFUMX
select -assert-count 6 t:TRELLIS_FF
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D

8
tests/arch/efinix/fsm.ys
View file

@ -2,9 +2,11 @@ read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

13
tests/arch/ice40/fsm.ys
View file

@ -2,12 +2,15 @@ read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 4 t:SB_DFF
select -assert-count 2 t:SB_DFFESR
select -assert-count 2 t:SB_DFFSR
select -assert-count 1 t:SB_DFFSS
select -assert-count 13 t:SB_LUT4
select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
select -assert-count 15 t:SB_LUT4
select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D

6
tests/arch/xilinx/fsm.ys
View file

@ -2,7 +2,11 @@ read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module