mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

memory_libmap: Tweak whitespace

Browse source
This commit is contained in:
Martin Povišer 2023-09-04 14:48:49 +02:00
parent 73cb4977b2
commit 3de84b959f
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
passes/memory/memory_libmap.cc
View file

@ -667,7 +667,7 @@ void MemMapping::assign_wr_ports() {
if (used >= GetSize(pg.names)) { if (used >= GetSize(pg.names)) {
log_reject(*cfg.def, pg, "not enough unassigned ports remaining"); log_reject(*cfg.def, pg, "not enough unassigned ports remaining");
continue; continue;
} }
for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) { for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) {
auto &def = pg.variants[pvi]; auto &def = pg.variants[pvi];
// Make sure the target is a write port. // Make sure the target is a write port.
@ -2114,7 +2114,7 @@ struct MemoryLibMapPass : public Pass {
log(" memory_libmap -lib <library_file> [-D <condition>] [selection]\n"); log(" memory_libmap -lib <library_file> [-D <condition>] [selection]\n");
log("\n"); log("\n");
log("This pass takes a description of available RAM cell types and maps\n"); log("This pass takes a description of available RAM cell types and maps\n");
log("all selected memories to one of them, or leaves them to be mapped to FFs.\n"); log("all selected memories to one of them, or leaves them to be mapped to FFs.\n");
log("\n"); log("\n");
log(" -lib <library_file>\n"); log(" -lib <library_file>\n");
log(" Selects a library file containing RAM cell definitions. This option\n"); log(" Selects a library file containing RAM cell definitions. This option\n");