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Separate check for ff's types

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This commit is contained in:
Miodrag Milanovic 2019-10-04 12:48:27 +02:00
parent 286a272872
commit 3de7889d08
2 changed files with 50 additions and 49 deletions
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40
tests/efinix/adffs.v
View file

@ -45,43 +45,3 @@ module ndffnr
else else
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
dffs u_dffs (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnr u_ndffnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule

59
tests/efinix/adffs.ys
View file

@ -1,12 +1,53 @@
read_verilog adffs.v read_verilog adffs.v
proc design -save read
#async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
equiv_opt -multiclock -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
proc
hierarchy -top adff
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_GBUFCE
select -assert-count 4 t:EFX_FF
select -assert-count 2 t:EFX_LUT4 select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top adffn
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
proc
hierarchy -top dffs
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D